Lattice Semiconductor ECP5 Technical Notes
Also see for ECP5 Versa: User guideUser guideUser guideTechnical noteUsage Guide
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www.latticesemi.com 1 TN1265_1.1November 2015 Technical Note TN1265© 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brandor product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.IntroductionECP5 TM and ECP5-5GTM devices support high-speed I/O interfaces, including Double Data Rate (DDR) and SingleData Rate (SDR) interfaces, using the logic built into the Programmable I/O (PIO). SDR applications capture dataon one edge of a clock while DDR interfaces capture data on both the rising and falling edges of the clock, thusdoubling the performance. ECP5 and ECP5-5G device I/Os also have dedicated circuitry that is used along withthe DDR I/O to support DDR2, DDR3, DDR3L, LPDDR2 and LPDDR3 SDRAM memory interfaces.This document discusses how to utilize the capabilities of the ECP5 and ECP5-5G devices to implement high-speed generic DDR interface and the DDR memory interfaces. Refer to the Implementing DDR Memory Interfacessection of this document for more information.External Interface DescriptionThis technical note uses two types of external interface definitions, centered and aligned. A centered external inter-face means that, at the device pins, the clock is centered in the data opening. An aligned external interface meansthat, at the device pins, the clock and data transition are aligned. This is also sometimes called edge-on-edge.Figure 1 shows the external interface waveform for SDR and DDR.Figure 1. External Interface DefinitionsThe interfaces described are referenced as centered or aligned interfaces. An aligned interface will need to adjustthe clock location to satisfy the capture flip-flop setup and hold times. A centered interface will need to balance theclock and data delay to the first flip-flop to maintain the setup and hold already provided.SDR AlignedDDR AlignedSDR CenteredDDR CenteredECP5 and ECP5-5GHigh-Speed I/O Interface |
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