ZCU106 BoardInterface TestDecember 2018XTP491

Xilinx ZCU106 Manual

Revision History

Overview

Block Diagram

Board Features

Board Specifications

Environmental

Board Component Location

Default Jumper and Switch Settings

Jumpers

Switches

Installing the ZCU106 Board in a PC Chassis

MPSoC Device Configuration

Quad SPI

PS-Side: DDR4 SODIMM Socket

DDR4 Component Memory

PSMIO

Quad SPI Flash Memory (MIO 0–12)

USB 3.0 Transceiver and USB 2.0 ULPI PHY

SD Card Interface

Programmable Logic JTAG Programming Options

EMIO ARM Trace Port

Clock Generation

MHz Tri-Speed Ethernet PHY

Ethernet PHY Reset

CP2108 USB UART Interface

HDMI Video Output

HDMI Clock Recovery

SDI Video

AES3 Audio

SFP/SFP+ Connectors

SFP/SFP+ Clock Recovery

User PMOD GPIO Headers

Prototype Header

User I2C0 Receptacle

User I/O

Power and Status LEDs

GTH Transceivers

PCI Express Endpoint Connectivity

PS GTR Transceivers

FPGA Mezzanine Card Interface

FMC HPC1 Connector J4

Cooling Fan Connector

VADJ_FMC Power Rail

Board Power System

Monitoring Voltage and Current

Safety

Xilinx Resources

References

Please Read: Important Legal Notices

ZCU106

quick start guide

About this TRD

Zynq UltraScale+ MPSoC Overview

key features

Design Modules

Design Components

Introduction

Software Architecture

GUI Application (vcu_qt)

demo mode

GStreamer Application (vcu_gst_app)

GStreamer Interface Library (vcu_gst_lib)

AXI Performance Monitor (APM) Library (vcu_apm_lib)

Boot Process

Clocking

Reset

Video Pipelines

Address Map

Interrupt Map

Descriptions