NXP Semiconductors 56800E manuals
56800E
Table of contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Online UPS Designer Reference Manual,
- Introduction
- DC-to-DC Converters
- Rail Ripple
- System Overview
- System Actuators
- Input Rectifier Theory of Operation
- Rectifier Soft Start
- Full Wave-Controlled Rectifier Bridge
- Power Factor Corrector (PFC) Theory of Operation
- PFC Current and Voltage Waveforms
- PFC Schematic
- Resulting Parallel Connection between C3 and C7
- Battery Charger Theory of Operation
- Battery Booster Theory of Operation
- Drive Signals for Battery Booster Switches
- Inverter Theory of Operation
- Pulse Width Modulation
- Power Supplies and Isolation Circuitry
- Waveforms at A and B
- Current Waveforms
- Sensing Circuits and Reference Voltage Generator
- Partial View of the Auxiliary Power Supply and Optoisolation Network
- Voltage Reference Supply
- Silicon Controlled Rectifier (SCR) Gate Drivers
- Power Transfer Circuits (Bypass) Theory of Operation
- Overcurrent Protection
- Overcurrent Protection for Rectifier and Inverter
- Battery Temperature Sensing
- Battery Temperature Sensor
- Control Algorithms Discrete Equivalents
- PFC and Rail Control
- PFC and Rail Control Loops (Positive Semicycle)
- Battery Charger Control
- Inverter Control
- Battery Booster Control Loop
- Minimizing Delay in the Control Loops
- F8346 Controller
- Reset/Modes/Clock
- Program And Data Memory
- RS-232 Serial Communications
- LCD Interface
- Peripheral Expansion Connectors
- A/D Ports Expansion Connectors
- GPIOPort C Expansion Connector (Bits 0—1)
- CAN Interface
- Debug Support
- Parallel JTAG Interface Connector
- A/D Filters
- Power Input
- External Power Input
- Panel Description
- Operation with EVM or Control Board
- Jumper Configuration for EVM and Control Board Operation
- Jumper Position for Configuration of the Power Board
- Functional Components and Location of Jumpers on the Power Board
- Jumpers on the Control Board
- Operation
- Turning the UPS On
- The Right Side of the UPS
- Peripheral and I/O Pins Assignment
- Main Execution Routine
- Main Routine Flow Diagram
- Interrupt Handlers
- Flow Diagram for the Interrupt Service Routine AD1_OnEnd (1 of 5)
- Flow Diagram for the Interrupt Service Routine AD1_OnEnd (2 of 5)
- Flow Diagram for the Interrupt Service Routing AD1_OnEnd (3 of 5)
- Flow Diagram for the Interrupt Service Routine AD1_OnEnd (4 of 5)
- Flow Diagram for the Interrupt Service Routine AD1_OnEnd (5 of 5)
- UPS Overcurrent Protection Interrupt Handlers
- Battery Temperature Reading
- Delay_Timer_OnInterrupt
- Inverter Control Loop
- PFC Control Loop
- Battery Charger Control Loop
- Phase Locked Loop Routine
- Control Loop
- Sine Wave Look-Up Table
- Frequency Measurement Routine
- Rectifier Soft Start Routine
- Root Mean Square (RMS) Sensing
- Power Sensing
- General Purpose Digital Filters Used in the Implementation
- High-Frequency Noise Rejection Filter
- Flash Memory Access
- Intrinsic 56800E Functions
- Connectivity Description
- Implementation
- Ethernet Abstraction Layer
- System Services Initialization
- Physical Layer Initialization
- Main Application
- Stack Loop
- Defines Used by Main Connectivity Loop
- Inverter Performance
- Inverter Voltage Harmonics Under No Load Conditions
- Inverter Voltage Harmonics Under Full Load Conditions—Battery Operated
- Inverter Transient Response to a Resistive Load (200W)
- PFC Performance Under Full Load Conditions
- PFC Performance at 59W Linear Load Conditions
- Frequence Performance
- Battery Charger Performance
- Bypass Switch Performance
- A.1 Control Board Schematics
- A.2 Power Board Schematics
- B.1 Specifications of Ferromagnetic Materials
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