Aaeon BOXER-6651 manuals
BOXER-6651
Table of contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- BOXER-6652
- Specifications
- Chapter 2 – Hardware Information
- Dimensions
- Jumpers and Connectors
- List of Jumpers
- Front Panel Connector (JP1)
- LVDS Port Operating VCC Selection (JP4)
- COM2 Pin9 Function Selection (JP11)
- COM4 TX/DTR Termination Selection (JP15)
- List of Connectors
- BIOS Debug Port (CN1)
- LVDS Port (CN3)
- USB 2.0 Port 4 and 5 (CN4)
- UIM Card Socket (Push-Push Type) (CN7)
- CFast Slot (CN9)
- COM Port 6 (Wafer Box, Optional) (CN10)
- COM Port 5 (Wafer Box, Optional) (CN11)
- PSON# Output (CN13)
- V Output for SATA HDD (CN16)
- MiniCard Slot (Half-MiniCard) (CN18)
- LPC Port (CN19)
- MiniCard Slot (Full-MiniCard) (CN20)
- Digital I/O Port (CN21)
- DDR3L SODIMM Slot (CN24)
- Audio I/O Port (CN28)
- LAN (RJ-45) + USB 3.0 + USB 2.0 (CN30)
- LAN (RJ-45) + Dual USB 2.0 (CN31)
- COM Port 3 and 4 (D-SUB 9) (CN32)
- Phone Jack for Line in/Out (CN33)
- COM Port 1 and 2 (D-SUB 9) (CN34)
- VGA + DVI-D Port (CN35)
- PWR LED/HDD LED (LED3)
- Inserting CFast Card
- Installing MiniCard
- Installing RAM
- Chapter 3 - AMI BIOS Setup
- System Test and Initialization
- AMI BIOS Setup
- Setup Submenu: Main
- Setup Submenu: Advanced
- Advanced: Power Management
- Power Management: RTC Wake Settings
- Advanced: CPU Configuration
- Advanced: IDE Configuration
- Advanced: USB Configuration
- Advanced: Trusted Computing
- Advanced: SIO Configuration
- 3.4.6.1 SIO Configuration: Serial Port 1/2/3/4/5/6 Configuration
- Advanced: Hardware Monitor
- Advanced: AMI Graphic Output Protocol Policy
- Setup submenu: Chipset
- Chipset: Intel IGD Configuration
- South Bridge
- Security
- Setup submenu: Boot
- Boot: BBS Priorities
- Setup submenu: Save & Exit
- Chapter 4 – Drivers Installation
- Product CD/DVD
- Appendix A - Watchdog Timer Programming
- A.1 Watchdog Timer Initial Program
- A.2 Watchdog Sample Program
- Appendix B - I/O Information
- B.1 I/O Address Map
- B.2 Memory Address Map
- B.3 IRQ Mapping Chart
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