Aaeon GENE-APL5 manuals
GENE-APL5
Table of contents
- copyright notice
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Chapter 1 - Product Specifications
- Specifications
- Chapter 2 – Hardware Information
- Dimensions
- Dimensions (Optional HDMI SKU)
- Jumpers and Connectors
- Jumpers and Connectors (Optional HDMI SKU)
- Block Diagram
- List of Jumpers
- LVDS Port 1 Backlight Inverter VCC Selection (JP1)
- COM3 Pin8 Function Selection (JP4)
- LVDS Port 2 Backlight Inverter VCC Selection (JP7)
- Clear CMOS Jumper (JP10)
- List of Connectors
- VSB Output w/SMBus (CN1)
- V Output for SATA HDD (CN3)
- External +5VSB Input (CN6)
- LVDS Port 1 (CN8)
- COM Port 2 (CN9)
- LPT Port or Digital I/O Port (CN10)
- LPC Port (CN11)
- COM Port 3 (CN12)
- BIOS Debug Port (CN13)
- PS/2 Keyboard/Mouse Combo Port (CN15)
- USB 2.0 Port 2 (CN16)
- COM Port 1 (CN18) (Wafer, Opional)
- USB 2.0 Port 5 (CN20)
- Touchscreen Connector (CN22)
- CPU Fan (CN23, Optional)
- USB 3.0 Ports 0 and 1 (CN25)
- LAN (RJ-45) Port 2 (CN26)
- COM Port 1 (CN28, D-SUB 9)
- Battery (CN30)
- VGA Port (CN31)
- Mini-Card Slot (Half-Mini) (CN33)
- mSATA (Full-Size) (CN34)
- Chapter 3 - AMI BIOS Setup
- System Test and Initialization
- AMI BIOS Setup
- Setup submenu: Main
- Setup submenu: Advanced
- Advanced: Trusted Computing
- Advanced: CPU Management
- Advanced: Hardware Monitor
- Configuration
- Advanced: SIO Configuration
- SIO Configuration: Serial Port 1 Configuration
- SIO Configuration: Serial Port 2 Configuration
- SIO Configuration: Serial Port 3 Configuration
- SIO Configuration: Serial Port 4 Configuration
- SIO Configuration: Parallel Port Configuration
- Advanced: Power Management
- Advanced: Digital IO Port Configuration
- Setup submenu: Chipset
- Chipset: North Bridge
- North Bridge: LVDS Panel Configuration
- Setup submenu: Security
- Setup submenu: Boot
- Setup submenu: Save & Exit
- Note for Users
- Chapter 4 – Drivers Installation
- Product CD/DVD
- Appendix A - Watchdog Timer Programming
- A.1 Watchdog Timer Registers
- A.2 Watchdog Sample Program
- Appendix B - I/O Information
- B.1 I/O Address Map
- B.2 Memory Address Map
- B.3 IRQ Mapping Chart
- Appendix C – Mating Connectors
- C.1 List of Mating Connectors and Cables
- Appendix D – Digital I/O Ports
- D.1 Digital I/O Register
- D.2 Digital I/O Sample Code (4 in 4 out, 2 low 2 high)
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