Document number 205065Version Rev EIssue date 2017-03-07Sirius OBC and TCM User Manualwww.aacmicrotec.com Page 118 of 1319. Connector interfaces9.1. JTAG-RTL, FPGA-JTAG connectorThe following pins are available on the ST60-10P connector, see Table 9-1.Table 9-1 - JTAG pin-outsPin # Signal name DescriptionPin 1 GND GroundPin 2 RTL-JTAG-TDI Test Data In, data shifted into the device.Pin 3 RTL-JTAG-TRSTB Test ResetPin 4 VCC_3V3 Power supplyPin 5 VCC_3V3 Power supplyPin 6 RTL-JTAG-TMS Test Mode SelectPin 7 Not connected -Pin 8 RTL-JTAG-TDO Test Data Out, data shifted out of the devicePin 9 GND GroundPin 10 RTL-JTAG-TCK Test Clock9.2. DEBUG-SWThe following pins are available on the ST60-18P, connector. See Table 9-2.Table 9-2 - Debug SW pin-outsPin # Signal name DescriptionPin 1 ETH-DEBUG-RESET ResetPin 2 GND GroundPin 3 ETH-DEBUG-SYNC Not availablePin 4 ETH-DEBUG-TX Not availablePin 5 ETH-DEBUG-RX Not availablePin 6 ETH-DEBUG-MDC Not availablePin 7 ETH-DEBUG-MDIO Not availablePin 8 ETH-DEBUG-CLK Not availablePin 9 GND GroundPin 10 DEBUG-JTAG-TDI Debug Test data inPin 11 DEBUG-JTAG-RX Debug UART RXPin 12 DEBUG-JTAG-TX Debug UART TXPin 13 VCC_3V3 Power supplyPin 14 DEBUG-JTAG-TMS Debug Test mode selectPin 15 VCC_3V3 Power supplyPin 16 DEBUG-JTAG-TDO Debug Test data outPin 17 ETH-DEBUG-DETECT Detect signal for the debugger