Table 49. Configurable logic blocksLogic block Quantitywith cycletimeRange or value Accuracy5 ms 20 ms 100 msAND 60 60 160 - -OR 60 60 160 - -XOR 10 10 20 - -INVERTER 30 30 80 - -SRMEMORY 10 10 20 - -RSMEMORY 10 10 20 - -GATE 10 10 20 - -PULSETIMER 10 10 20 (0.000–90000.000) s ± 0.5% ± 25 ms for 20ms cycle timeTIMERSET 10 10 20 (0.000–90000.000) s ± 0.5% ± 25 ms for 20ms cycle timeLOOPDELAY 10 10 20Table 50. Configurable logic Q/TLogic block Quantitywith cycletimeRange or value Accuracy20 ms 100 msANDQT 20 100 - -ORQT 20 100 - -XORQT 10 30 - -INVERTERQT 20 100 - -RSMEMORYQT 10 30 - -SRMEMORYQT 15 10 - -PULSETIMERQT 10 30 (0.000–90000.000) s± 0.5% ± 25 ms for 20 ms cycle timeTIMERSETQT 10 30 (0.000–90000.000) s± 0.5% ± 25 ms for 20 ms cycle timeINVALIDQT 6 6 - -INDCOMBSPQT 10 10 - -INDEXTSPQT 10 10 - -Table 51. Elapsed time integrator with limit transgression and overflow supervision TEIGGIOFunction Cycle time (ms) Range or value AccuracyElapsed time integration 5 0 ~ 999999.9 s ±0.05% or ±0.01 s20 0 ~ 999999.9 s ±0.05% or ±0.04 s100 0 ~ 999999.9 s ±0.05% or ±0.2 sTransformer protection RET650 1MRK 504 137-BEN BProduct version: 1.3ABB 51