ABOV SEMICONDUCTOR MC81F4204 User Manual
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MC81F420478 April 24, 2012 Ver.1.41INTFHINTERRUPT FLAG HIGH REGISTER 00EEH7 6 5 4 3 2 1 0INTFH T0MIF T0OVIF T1MIF T1OVIF T2MIF T2OVIF Reset value: 00HR/W R/W R/W R/W R/W R/W R/W R/W0: No generationT0MIF Timer 0 Match Interrupt Flag Bit 1: Generation0: No generationT0OVIF Timer 0 Overflow Interrupt Flag Bit 1: Generation0: No generationT1MIF Timer 1 Match Interrupt Flag Bit 1: Generation0: No generationT1OVIF Timer 1 Overflow Interrupt Flag Bit 1: Generation0: No generationT2MIF Timer 2 Match Interrupt Flag Bit 1: Generation0: No generationT2OVIF Timer 2 Overflow Interrupt Flag Bit 1: Generation- bit 1 – bit 0 Not used for MC81F4204Note:When you use ‘Shard Interrupt Vector’, those INTFH is used to recognize which interrupt isgenerated. See ‘11.4 Shared Interrupt Vector’ on page 81 for more information.11.2 Interrupt SequenceAn interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to “0” by areset or an instruction. Interrupt acceptance sequence requires 8 cycles of fXIN (1μs at fXIN=4MHz) after the completion of the current instruction execution. The interrupt service task isterminated upon execution of an interrupt return instruction [RETI].Interrupt acceptance1. The interrupt master enable flag (I-flag) is cleared to “0” to temporarily disable the acceptanceof any following maskable interrupts. When a non-maskable interrupt is accepted, theacceptance of any following interrupts is temporarily disabled.2. Interrupt request flag for the interrupt source accepted is cleared to “0”.3. The contents of the program counter (return address) and the program status word are saved(pushed) onto the stack area. The stack pointer decreases 3 times.4. The entry address of the interrupt service program is read from the vector table address andthe entry address is loaded to the program counter.5. The instruction stored at the entry address of the interrupt service program is executed. |
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