BIOS Setup 3-93-4. Advanced Chipset FeaturesPhoenix ñ Award WorkstationBIOS CMOS Setup UtilityAdvanced Chipset FeaturesHT Frequency AUTO Item Help► DRAM Configuration Press EnterSSE/SSE2 Instructions EnableSystem BIOS Cachable Disable↑↓:Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General HelpF5: Previous Values F6: Fail-Safe Defaults F7: Optimized DefaultsHT Frequency:This item selects the LDT Bus Frequency.# DRAM Configuration:Click key to enter its submenu:Phoenix ñ Award WorkstationBIOS CMOS Setup UtilityDRAM ConfigurationDRAM Timing Selectable Auto Item HelpX - DRAM Clock AutoX - CAS latency Time AutoX - Row Cycle Time AutoX - Row Refresh Cycle Time AutoX - Min RAS# Active time AutoX - RAS# to CAS# delay AutoX - RAS# Precharge Time AutoX - RAS# to RAS# delay AutoX - Write Recovery Time AutoX - Write to Read Delay AutoX - Read to Write Delay AutoX - DRAM Command rate AutoX - Read Preamble value AutoX - Max. Async Latency value AutoX - Bank Interleaving EnabledX - Burst Length 4 beatsX - DRAM Drive Strength DriveX - Force 64-bit mode always DisabledX - R/W Queue Bypass Counter. 8X - Bypass Max 4X - Idle Cycle Limit(ILD-Lmt) 16 CyclesX - Dynamic Idle Cycle Count. EnabledMTRR mapping mode Continuous32 bit Dram Memory Hole Auto↑↓:Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General HelpF5: Previous Values F6: Fail-Safe Defaults F7: Optimized DefaultsUserís Manual
