Acer Altos R510 Service Manual

Also see for Altos R510: User guide

Contents

Acer Altos R510 Service Manual Manual pdf 115 page image

Chapter 4 108that logging for that type of error has been disabled. Such an entry indicates a serious hardware problem thatmust be repaired at the earliest possible time.The system BIOS implements this feature for two types of errors, correctable memory errors and correctablebus errors. If ten errors occur in a single wall-clock hour, the corresponding error handler disables furtherreporting of that type of error. A unique counter is used for each type of error; i.e., an overrun of memoryerrors does not affect bus error reporting.The BIOS re-enables logging and SMIs the next time the system is rebooted.Error LoggingThis section defines how errors are handled by the system BIOS. Also discussed is the role of the BIOS inerror handling and the interaction between the BIOS, platform hardware, and server management firmwarewith regard to error handling. In addition, error-logging techniques are described and beep codes for errors aredefined.One of the major requirements of server management is to correctly and consistently handle system errors.System error sources can be categorized as follows:T PCI busT Memory multi-bit errors (single-bit errors are not logged)T SensorsT Processor internal errors, bus/address errors, thermal trip errors, temperatures and voltages, andGTL voltage levelsT Errors detected during POST, logged as POST errorsSensors are managed by the mBMC. The mBMC is capable of receiving event messages from individualsensors and logging system eventsSMI HandlerThe SMI handler handles and logs system-level events that are not visible to the server managementfirmware. If SEL error logging is disabled in the BIOS Setup utility, no SMI signals are generated on systemerrors. If error logging is enabled, the SMI handler preprocesses all system errors, even those that arenormally considered to generate an NMI.The SMI handler sends a command to the mBMC to log the event and provides the data to be logged. Forexample, The BIOS programs the hardware to generate an SMI on a single-bit memory error and logs thelocation of the failed DIMM in the system event log.PCI Bus ErrorThe PCI bus defines two error pins, PERR# and SERR#, for reporting PCI parity errors and system errors,respectively. The BIOS can be instructed to enable or disable reporting the PERR# and SERR# through NMI.Disabling NMI for PERR# and/or SERR# also disables logging of the corresponding event. In the case ofPERR#, the PCI bus master has the option to retry the offending transaction, or to report it using SERR#. Allother PCI-related errors are reported by SERR#. All the PCI-to-PCI bridges are configured so that theygenerate a SERR# on the primary interface whenever there is a SERR# on the secondary side, if SERR# hasbeen enabled through Setup. The same is true for PERR#.Processor Bus ErrorIf the chipset supports ECC on the processor bus then the BIOS enables the error correction and detectioncapabilities of the processors by setting appropriate bits in the processor model specific register (MSR) andappropriate bits inside the chipset.In the case of irrecoverable errors on the host processor bus, proper execution of the asynchronous errorhandler (usually SMI) cannot be guaranteed and the handler cannot be relied upon to log such conditions.The handler will record the error to the SEL only if the system has not experienced a catastrophic failure thatcompromises the integrity of the handler.