Chapter 4 145POST Codes TablesThese tables describe the POST codes, drivers, and keys for the POST.SecNO_EVICTION_MODE_DEBUG EQU 1 (CommonPlatform\sec\Ia32\SecCore.inc)Memory:DEBUG_BIOS equ 1 (Chipset\Alviso\MemoryInitAsm\IA32\IMEMORY.INC)Code Description0xC2 MTRR setup0xC3 Enable cache0xC4 Establish cache tags0xC5 Enter NEM, Place the BSP in No Fill mode, set CR0.CD = 1, CR0.NW = 0.0xCF Cache Init FinishedCode Description0xA0 First memory check point0x01 Enable MCHBAR0x02 Check for DRAM initialization interrupt and reset fail0x03 Verify all DIMMs are DDR or DDR2 and unbuffered0x04 Detect an improper warm reset and handle0x05 Detect if ECC SO-DIMMs are present in the system0x06 Verify all DIMMs are single or double sided and not asymmetric0x07 Verify all DIMMs are x8 or x16 width0x08 Find a common CAS latency between the DIMMS and the MCH0x09 Determine the memory frequency and CAS latency to program0x10 Determine the smallest common TRAS for all DIMMs0x11 Determine the smallest common TRP for all DIMMs0x12 Determine the smallest common TRCD for all DIMMs0x13 Determine the smallest refresh period for all DIMMs0x14 Verify burst length of 8 is supported by all DIMMs0x15 Determine the smallest tWR supported by all DIMMs0x16 Determine DIMM size parameters0x17 Program the correct system memory frequency0x18 Determine and set the mode of operation for the memory channels0x19 Program clock crossing registers0x20 Disable Fast Dispatch0x21 Program the DRAM Row Attributes and DRAM Row Boundary registers0x22 Program the DRAM Bank Architecture register0x23 Program the DRAM Timing & and DRAM Control registers0x24 Program ODT0x25 Perform steps required before memory init0x26 Program the receive enable reference timing control registerProgram the DLL Timing Control Registers, RCOMP settings
