Chapter 4 139Core POST Code TableThe following table details the core POST codes and functions used in SecureCore.0xA0xx Launch BIOS ACMSclean PEI chipset/MRC0xA4xx Launch BIOS ACMScheck PEI chipset/MRC0xE5 Wait for ME ready DXE HECI/iAMT0xE6 ME Ready DXE HECI/iAMTPOSTCode Function Phase Component0x00 Early Microcode update for CAR CEI / SEC Core0x01 Enable CAR CEI / SEC Core0x02 CAR Done, initial stack CEI / SEC Core0xEE unknown CPU ID to load uCode CEI / SEC CPU0xEF unknown DT CPU to load uCode CEI / SEC CPU0xnn File count found in a volume PEI Core0x11 Debug Test driver for debug test PPI 1 (If install debugTestdriver)PEI Core0x22 Debug Test driver for debug test PPI 2 (If install debugTestdriver)PEI Core0x33 Debug Test driver for debug test PPI 3 (If install debugTestdriver)PEI Core0x44 Entry point of loadfile PEI Core0x88 Entry point of apMuLoader PEI Core0x80 A PEIM found PEI Core0x82 PEIM not dispatched yet PEI Core0x84 PEIM satisfies depex PEI Core0x86 Image loaded but fail on security PEI Core0x88 Executing a PEIM PEI Core0x8A Processing notify event for newly installed PPI PEI Core0x8C Handing off to next phase (DXE) PEI Core0x8F Fail to hand off to next phase, system halt PEI Core0x90 All PEIM dispatched! Going to DxeIpl PEI Core0xCC AP Micro-code update PEI Core0x20 S3 resume entry S3 resume Core0x21 Start running Boot-time bootscripts S3 resume Core0x22 Start running Run-time bootscripts S3 resume Core0x23 End of S3 resume, jump back to Waking vector S3 resume Core0x80 Initialize the chipset Crisis Recovery Core0x81 Initialize the bridge Crisis Recovery Core0x82 Initialize the CPU Crisis Recovery Core0x89 Set Huge Segment Crisis Recovery Core0x83 Initialize system timer Crisis Recovery Core0x84 Initialize system I/O Crisis Recovery Core0x88 Initialize Multi Processor Crisis Recovery CorePOST Code Function Phase Component
