Chapter 4 137POST Codes TablesThese tables describe the POST codes, drivers, and keys for the POST.Chipset POST CodesThe following table details the Chipset POST codes and components used in the POST.POST Code Function Phase Component0xA0 MRC Entry PEI chipset/MRC0x01 Enable MCHBAR PEI chipset/MRC0x02 Check ME existence PEI chipset/MRC0x03 Check for DRAM initialization interrupt and reset fail PEI chipset/MRC0x04 Determine the system Memory type based on first populatedsocketPEI chipset/MRC0x05 Verify all DIMMs are DDR2 and SO-DIMMS, which areunbufferedPEI chipset/MRC0x06 Verify all DIMMs are Non-ECC PEI chipset/MRC0x07 Verify all DIMMs are single or double sided and not mixed PEI chipset/MRC0x08 Verify all DIMMs are x8 or x16 width PEI chipset/MRC0x09 Calculate number of Row and Column bits PEI chipset/MRC0x10 Calculate number of banks for each DIMM PEI chipset/MRC0x11 Determine raw card type PEI chipset/MRC0x12 Find a common CAS latency between the DIMMS and theMCHPEI chipset/MRC0x13 Determine the memory frequency and CAS latency to program PEI chipset/MRC0x14 Determine the smallest common timing value for all DIMMS PEI chipset/MRC0x17 Power management resume PEI chipset/MRC0x18 Program DRAM type (DDR2/DDR3) and Power up sequence PEI chipset/MRC0x19 Program the correct system memory frequency PEI chipset/MRC0x20 Program the correct Graphics memory frequency PEI chipset/MRC0x21 Early DRC initialization PEI chipset/MRC0x22 Program the DRAM Row Attributes and DRAM Row Boundaryregisters PRE JEDEC.PEI chipset/MRC0x23 Program the RCOMP SRAM registers PEI chipset/MRC0x24 Program DRAM type (DDR2/DDR3) and Power up sequence PEI chipset/MRC0x25 Program the DRAM Timing PEI chipset/MRC0x26 Program the DRAM Bank Architecture register PEI chipset/MRC0x27 Enable all clocks on populated rows PEI chipset/MRC0x28 Program MCH ODT PEI chipset/MRC0x29 Program tRD PEI chipset/MRC0x30 Miscellaneous Pre JEDEC steps PEI chipset/MRC0x31 Program clock crossing registers PEI chipset/MRC0x32 Program the Egress port timings PEI chipset/MRC0x33 Program the Memory IO registers PEI chipset/MRC0x34 Perform steps required before JEDEC PEI chipset/MRC0x35 Perform JEDEC memory initialization for all memory rows PEI chipset/MRC
