Acer RL70 Service Manual

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Acer RL70 Service Manual Manual pdf 79 page image

51 Chapter 4CheckpointsA checkpoint is either a byte or word value output to I/O port 80h.The BIOS outputs checkpoints throughoutbootblock and Power-On Self Test (POST) to indicate the task the system is currently executing. Checkpointsare very useful in aiding software developers or technicians in debugging problems that occur during the pre-boot process.Viewing BIOS checkpointsViewing all checkpoints generated by the BIOS requires acheckpoint card, also referred to as a POST card orPOST diagnostic card. These are ISA or PCI add-in cards that show the value of I/O port 80h on a LEDdisplay. Checkpoints may appear on the bottom right corner of the screen during POST. This display methodislimited, since it only displays checkpoints thatoccur after the video card has been activated.Bootblock Initialization Code CheckpointsThe Bootblock initialization code sets up the chipset,memory, and other components before system memory isavailable. The following table describes the type of checkpoints that may occur during the bootblockinitialization portion of the BIOS.NOTE: Please note that checkpoints may differ between different platforms based on systemconfiguration.Checkpoints may change due to vendor requirements,system chipset or option ROMsfrom add-in PCI devices.Checkpoint DescriptionBefore D1 Early chipset initialization is done. Early super I/O initialization is done includingRTC andkeyboard controller. NMI is disabled.D0 Go to flat mode with 4GB limit and GA20 enabled. Verify the bootblock checksum.D1 Perform keyboard controller BAT test. Check if waking up from power managementsuspendstate. Save power-onCPUID value in scratch CMOS.D2 Disable CACHE before memory detection. Execute full memory sizing module.Verify that flatmode is enabled.D3 If memory sizing module not executed, start memory refresh and do memory sizinginBootblock code. Do additional chipsetinitialization. Re-enable CACHE. Verifythat flat modeis enabled.D4 Test base 512KB memory. Adjust policies and cache first 8MB. Set stack.D5 Bootblock code is copied from ROM to lower system memory and control is given toit. BIOSnow executes out of RAM.D6 Both key sequence and OEM specific method is checked to determine if BIOSrecovery isforced. Main BIOS checksum is tested. If BIOS recovery is necessary,control flows tocheckpoint E0. See Bootblock Recovery Code Checkpoints sectionfor more information.D7 Restore CPUID value back into register. The Bootblock-Runtime interface module is movedto system memory and control is given to it. Determine whether to execute serial flash.D8 The Runtime module is uncompressed into memory. CPUID information is stored in memory.D9 Store the Uncompressed pointer for future use in PMM. Copying Main BIOS into memory.Leaves all RAM below 1MB Read-Write including E000 and F000 shadow areas but closingSMRAM.DA Restore CPUID value back into register. Give control to BIOS POST (ExecutePOSTKernel).See POST Code Checkpoints section of document for more information.