26 Chapter 2Advanced Chipset FeaturesParameter Description OptionsCAS Latency TIme When synchronous DRAM is installed, the number of clockcycles of CAS latency depends on the DRAM timing.5,4,3,6,AutoDRAM RAS# to CAS# Delay This field lets you insert a timing delay between the CASand RAS strobe signals, used when DRAM is written to,read from, or refreshed, Fast gives faster performance; andSlow gives more stable performance. This field applies onlywhen synchronous DRAM is installed in the system.2,3,4,5,6,AutoDRAM RAS# PrechargeTImeIf an insufficient number of cycles is allowed for the RAS toaccumulate its charge before DRAM refresh, the refreshmay be incomplete and the DRAM may fail to retain data.Fast fives faster performance; and Slow gives more stableperformance.This field applies only when synchronousDRAM is installed in the syste.2,3,4,5,6,AutoPrecharge Delay This option is used to set up the timing delay between theSDRAM active to precharge.4,5,6,7,8,9,10,11,12,AutoOn Chip Memory Size Select the on chip memory size for VGA drive use.PEG/Onchip VGA Control This option is used to control the VGA Onchip VGAPEG PortAutoDVMT Mode This option is used to select the video mode. Fixed,DVMT,BothDRAM Timing Selectable By SPDx CAS Latency Time Autox DRAM RAS# Precharge AutoF6:Load Optimized Defaults F7:Load Fail-Safe DefaultsPEG/Onchip VGA Control [Auto]** VGA Setting **XOn-chip Video Memory Size [Press Enter]KLIJ :Move Enter: Select +/-/ :Value ESC:Exit F1:General HelpDVMT Mode [DVMT]Phoenix - AwardBIOS CMOS Setup UtilityAdvanced Chipset Featuresx DRAM RAS# to CAS# Delay Autox Precharge delay (tRAS) AutoSLP_S4# Assertion Width 4 to 5 Sec.Help ItemMenu Level X