Daewoo Color Television Service Manual

Contents

Daewoo Color Television Service Manual Manual pdf 28 page image

The vertical synchronisation is realised by means of a divider circuit. The vertical ramp generator needs an externalresistor and capacitor. For the vertical drive a differential output current is available. The outputs are DC coupled to thevertical output stage.The following geometry parameters can be adjusted:• Horizontal shift• Vertical amplitude• Vertical slope• S-correction• Vertical shiftChroma and luminance processingThe chroma band-pass and trap circuits (including the SECAM cloche filter) are realised by means of gyrators and aretuned to the right frequency by comparing the tuning frequency with the reference frequency of the colour decoder. Theluminance delay line and the delay cells for the peaking circuit are also realised with gyrators. The circuit contains a blackstretcher functi on which corrects the black level for incoming signals which have a difference between the black level andthe blanking level.Colour decoderThe ICs can decode PAL, NTSC and SECAM signals. The PAL/NTSC decoder does not need external referencecrystals but has an internal clock generator which is stabilised to the required frequency by using the 12 MHz clock signalfrom the referenc oscillator of the μ-Controller/Teletext decoder.The Automatic Colour Limiting (ACL) circuit (switchable via the ACL bit in subaddress 2OH) prevents oversaturationoccurring when signals with a high chroma-to-burst ratio are received. The ACL circuit is designed such that it onlyreduces the chroma signal and not the burst signal. This has the advantage that the colour sensitivity is not affected bythis function.SOFTWARE CONTROLThe CPU communicates with the peripheral functions using Special function Registers (SFRS) which are addressed asRAM locations. The registers for the Teletext decoder appear as normal SFRs in the μ-Controller memory map and arewritten to these functions by using a serial bus. This bus is controlled by dedicated hardware which uses a simplehandshake system for software synchronisation.For compatibility reasons and possible re-use of software blocks, the TV processor is controlled by I2C bus. The TVprocessor control registers cannot be read. Only the status registers can be read ( Read address 8A ).The SECAM decoder contains an auto-calibrating PLL demodulator which has two references, via the divided 12 MHzreference frequency (obtained from the μ-Controller) which is used to tune the PLL to the desired free-running frequencyand the bandgap reference to obtain the correct absolute value of the output signal. The VCO of the PLL is calibratedduring each vertical blanking period, when the IC is in search or SECAM mode.The base-band delay line (TDA 4665 function) is integrated. This delay line is also active during NTSC reception, toobtain a good suppression of cross colour effects. The demodulated colour difference signals are internally supplied tothe delay line.2FUNCTIONAL DESCRIPTION APPENDIX