Dell External OEMR XL R210II Technical Manual

Dell External OEMR XL R210II Technical Manual Manual pdf 35 page image

DellPowerEdge R210 Technical Guide 358.7 Low Pin Count (LPC) InterfaceThe Ibex Peak implements an LPC Interface as described in the LPC 1.1 Specification. The LowPin Count (LPC) bridge function of the Ibex Peak resides in PCI Device 31:Function 0. Inaddition to the LPC bridge interface function, D31:F0 contains other functional units includingDMA, interrupt controllers, timers, power management, system management, GPIO, and RTC.8.8 Serial Peripheral Interface (SPI)The Ibex Peak implements an SPI Interface as an alternative interface for the BIOS flash device.An SPI flash device can be used as a replacement for the FWH, and is required to supportGigabit Ethernet, Intel® Active Management Technology and integrated Intel Quiet SystemTechnology. The Ibex Peak supports up to two SPI flash devices with speed up to 20 MHz, 33MHz utilizing two chip select pins.8.9 Compatibility ModuleThe DMA controller incorporates the logic of two 82C37 DMA controllers, with sevenindependently programmable channels. Channels 0–3 are hardwired to 8-bit, count-by-bytetransfers, and channels 5–7 are hardwired to 16-bit, count-by-word transfers. Any two of theseven DMA channels can be programmed to support fast Type-F transfers.Channel 4 is reserved as a generic bus master request.The Ibex Peak supports LPC DMA, which is similar to ISA DMA, through the Ibex Peak’s DMAcontroller. LPC DMA is handled through the use of the LDRQ# lines from peripherals and specialencoding on LAD[3:0] from the host. Single, Demand, Verify, and Increment modes aresupported on the LPC interface.The timer/counter block contains three counters that are equivalent in function to those foundin one 82C54 programmable interval timer. These three counters are combined to provide thesystem timer function, and speaker tone. The 14.31818 MHz oscillator input provides the clocksource for these three counters.The Ibex Peak provides an ISA-Compatible Programmable Interrupt Controller (PIC) thatincorporates the functionality of two, 82C59 interrupt controllers. The two interruptcontrollers are cascaded so that 14 external and two internal interrupts are possible. Inaddition, the Ibex Peak supports a serial interrupt scheme.All of the registers in these modules can be read and restored. This is required to save andrestore system state after power has been removed and restored to the platform.8.10 Advanced Programmable Interrupt Controller (APIC)In addition to the standard ISA compatible Programmable Interrupt controller (PIC) described inthe previous section, the Ibex Peak incorporates the Advanced Programmable InterruptController (APIC).8.11 USB InterfaceThe Ibex Peak contains up to two Enhanced Host Controller Interface (EHCI) host controllersthat support USB high-speed signaling. High-speed USB 2.0 allows data transfers up to 480 Mb/swhich is 40 times faster than full-speed USB. The Ibex Peak also contains up to seven UniversalHost Controller Interface (UHCI) controllers that support USB full-speed and low-speed signaling.The Ibex Peak supports up to fourteen USB 2.0 ports. All fourteen ports are high-speed, full-speed, and low-speed capable. Ibex Peak’s port-routing logic determines whether a USB port iscontrolled by one of the UHCI or EHCI controllers.