Dell PowerEdge M710 Technical Manualbook

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Dell PowerEdge M710 Technical Manualbook Manual pdf 17 page image

Dell™ PowerEdge™ M710 Technical Guidebook17b. DiMMs supportedThe DDR3 memory interface consists of three channels, with up to two RDIMMs or UDIMMs per chan-nel for single-/dua- rank and up to two RDIMMs per channel for quad rank. The interface uses 2GB, 4GB,or 8GB RDIMMs. 1GB or 2GB UDIMMs are also supported. The memory mode is dependent on how thememory is populated in the system:Three channels per CPU populated identically• Typically, the system will be set to run in Memory Optimized (Independent Channel) mode inthis configuration. This mode offers the most DIMM population flexibility and system memorycapacity, but offers the least number of RAS (reliability, availability, service) features.• All three channels must be populated identically.• Users wanting memory sparing must also populate the DIMMs in this method, but one channelis the spare and is not accessible as system memory until it is brought online to replace a failingchannel.• The first two channels per CPU populated identically with the third channel unused• Typically, two channels operate in Advanced ECC (Lockstep) mode with each other byhaving the cache line split across both channels. This mode provides improved RASfeatures (SDDC support for x8-based memory).• For Memory Mirroring, two channels operate as mirrors of each other — writes go toboth channels and reads alternate between the two channels.• One channel per CPU populated• This is a simple Memory Optimized mode. No mirroring or sparing is supported.The PowerEdge M710 memory interface supports memory demand and patrol scrubbing, single-bitcorrection and multi-bit error detection. Correction of a x4 or x8 device failure is also possible withSDDC in the Advanced ECC mode. Additionally, correction of a x4 device failure is possible in theMemory Optimized mode. If DIMMs of different speeds are mixed, all channels will operate at the fastestcommon frequency. RDIMMs and UDIMMs cannot be mixed.• If memory mirroring is enabled, identical DIMMs must be installed in the same slots across bothchannels.• The third channel of each processor is unavailable for memory mirroring.• The first DIMM slot in each channel is color-coded with white ejection tabs for ease ofinstallation.• The DIMM sockets are placed 450 mils (11.43 mm) apart, center-to-center in order to provideenough space for sufficient airflow to cool stacked DIMMs.• The PE M710 memory system supports up to 18 DIMMs. DIMMs must be installed in each channelstarting with the DIMM farthest from the processor. Population order will be identified by thesilkscreen designator and the System Information Label (SIL) located on the chassis cover.• Memory Optimized: {1, 2, 3}, {4, 5, 6}, {7, 8, 9}• Advanced ECC or Mirrored: {2, 3}, {5, 6}, {8, 9}• Quad Rank or UDIMM: {1, 2, 3}, {4, 5, 6}, {7, 8, 9}c. speedMemory Speed LimitationsThe memory frequency is determined by a variety of inputs:• Speed of the DIMMs• Speed supported by the CPU• Configuration of the DIMMs