148LAN8700-AEZG-TR (HDMI : IC14)LAN8700-AEZG-TR Block DiagramnINT/TX_ER/TXD4MDCCRS/PHYAD4MDIOnRSTTX_ENVDD_COREVDD33LINK/PHYAD1ACTIVITY/PHYAD2FDUPLEX/PHYAD3XTAL2CLKIN/XTAL1RXD3/nINTSELRXD1/MODE1RXD2/MODE2TXD3RX_CLK/REGOFFTX_CLKRX_ER/RXD4VDDIOTXD1TXD0TXD2COL/RMII/CRS_DVTXPRXNVDDA3.3EXRES1VDDA3.3RXPVDDA3.3USB3300Hi-Speed USB2ULPI PHY32 Pin QFN12345678LAN8700/LAN8700IMII/RMII Ethernet PHY36 Pin QFNGND FLAG101112131415162423222120193231302928SPEED100/PHYAD0 VD_XR9RXD0/MODE017TXN182726253635343310M RxLogic100M RxLogicDSP System:ClockData RecoveryEqualizerAnalog-to-Digital100M PLLSquelch &Filters10M PLLReceive SectionCentralBiasHP Auto-MDIXManagementControlSMIRMII / MII LogicTXP / TXNTXD[0..3]TX_ENTX_ERTX_CLKRXD[0..3]RX_DVRX_ERRX_CLKCRSCOL/CRS_DVMDCMDIOSPEED100LINKACTIVITYFDUPLEXLED CircuitryMODE ControlnINTnRST RXP / RXN10M TxLogic10MTransmitter100M TxLogic100MTransmitterTransmit SectionPLL XTAL1XTAL2MODE0MODE1MODE2PHYAddressLatchesPHYAD[0..4]Auto-NegotiationInterruptGeneratorMIIMDIXControl