Denon DN-D6000 Service Manual

Also see for DND6000 - Dual DJ CD Player: Operating instructions Operating instructions Operating instructions

Contents

16DN-D600040 GND GND - - - - - GND41 GND GND - - - - - GND42 GND GND - - - - - GND43 GND GND - - - - - GND44 GND GND - - - - - GND45 VDDEXT VDDEXT I - - - - I/O power supply (+3.3V)46 PF5 DSPF3 O - - L - Programmable flag 5, Flag 3 to μcom (RESERVE)47 PF4 DSPF2 O - - L - Programmable flag 4, Flag 2 to μcom (RESERVE)48 PF3 DSPF1 O - - L - Programmable flag 3, Flag 1 to μcom (RESERVE)49 PF2 DSPF0 O - - L - Programmable flag 2, Flag 0 to μcom (RESERVE)50 PF1 DTIME O - - L - Programmable flag 1, Clock for playback output51 PF0 BTEND O - Pd L L Programmable flag 0, All end : H52 VDDINT VDDINT I - - - - Core power supply (+1.2V)53 SCK O - - L - Master slave clock54 MISO O - - L - Master in slave out55 MOSI O - - L - Master out slave in56 GND GND - - - - - GND57 VDDEXT VDDEXT I - - - - I/O power supply (+3.3V)58 DT1SEC O - - L - Playback data send 159 DT1PRI DDATA I - - - - Digital out data send 0 (serial port OUT 1)60 TFS1 DLRCK I - IPu - H Digital out send frame sync (LRCK) signal (serial port OUT 1)61 TSCLK1 DBCK I - - - - Digital out send frame sync (BCK) signal (serial port OUT 1)62 DR1SEC I - - L L Playback data receive 163 DR1PRI I - - L L Playback data receive 064 RFS1 O - - L - Receive frame sync (LRCK) signal (serial port IN 1)65 RSCLK1 O - - L - Receive frame sync (BCK) signal (serial port IN 1)66 VDDINT VDDINT I - - - - Core power supply (+1.2V)67 DT0SEC O - - L - Playback data send 168 DT0PRI ADATA I - - - - Analog playback data send 0 (serial port OUT 0)69 TFS0 ALRCK I - IPu - H Analog playback send frame sync (LRCK) signal (serial port OUT 0)70 GND GND - - - - - GND71 VDDEXT VDDEXT I - - - - I/O power supply (+3.3V)72 TSCLK0 ABCK I - - - - Analog playback send frame sync (BCK) signal (serial port OUT 0)73 DR0SEC I - - L L Playback data receive 174 DR0PRI SRDATA I - - - - Playback data receive 0 (serial port IN 0)75 RFS0 LRCK O - - - - Receive frame sync (LRCK) signal (serial port IN 0)76 RSCLK0 BCLK I - IPu - H Receive frame sync (BCK) signal (serial port IN 0)77 TMR2 O - - L - Timer 278 TMR1 O - - L - Timer 179 TMR0 O - - L - Timer 080 VDDINT VDDINT I - - - - Core power supply (+1.2V)81 TX TX O - - H - UART send82 RX RX I - Pu - H UART receive83 _EMU _EMU O - - - - Emulation status84 _TRST _TRST I - Pd - L Test reset (JTAG)85 TMS TMS I - Pu - H Test mode select (JTAG)86 TDI TDI I - Pu - H Test data input (JTAG)87 TD0 TD0 O - - - - Test data output (JTAG)88 GND GND - - - - - GND89 GND GND - - - - - GND90 GND GND - - - - - GND91 GND GND - - - - - GND92 GND GND - - - - - GND93 VDDEXT VDDEXT I - - - - I/O power supply (+3.3V)94 TCK TCK I - Pu - H Test clock (JTAG)PinNo. Pin Name Symbol I/O DET Ext Ini Res Functionwww. xiaoyu163. comQQ 376315150 992894298TEL 13942296513 992894298051513673QQTEL 13942296513 QQ 376315150 892498299TEL 13942296513 QQ 376315150 892498299http://www.xiaoyu163.comhttp://www.xiaoyu163.com