Denon DN-D9000 Service Manual

Also see for DN-D9000: Operating instructions Operating instructions Operating instructions

Contents

Denon DN-D9000 Service Manual Manual pdf 29 page image

29DN-D9000128M SDRAM(DS: IC302, 303, 402, 403)uPC1934GR-1JG-E1 (RC: IC310)4M FLASH MEMORY (M29W800AB)(DS: IC502, 509)W29EE011P (FG: IC507)1 5427 28TOP VIEWTOP VIEW12345678C TR TIN1II1FB 1DTC 1OUT 1GNDVREFDLYI N2I I2FB 2DTC 2OUT 2V CC161514131211109A0 - A16DQ0 - DQ7CEOEWEVDDGNDNCTerminal FunctionName FunctionAddress InputsData Inputs/OutputsChip EnableOutput EnableWrite EnablePower SupplyGroundNo ConnectionA1 A0A2 EA3 VSSA4 GA5 DQ0A6 DQ8A7 DQ1A17 DQ9A18 DQ2RB DQ10NC DQ3NC DQ11RP VCCW DQ4NC DQ12NC DQ5A8 DQ13A9 DQ6A10 DQ14A11 DQ7A12 DQ15A-1A13 VSSA14 BYTEA15 A16241312125363748TOPVIEW1234567891011121314 15 16 17 18 19 20212223242526272829303132A7A6A5A4A3A2A1A0DQ0DQ1DQ2GNDDQ3DQ4DQ5DQ6A14A13A8A9OEDQ7A12A15A16NCVDDWENCA10CEA11TOPVIEWCEOEWEDQ0:DQ7A0.......A16V DDV SSCONTROL OUTPUTBUFFERDECODER COREARRAYRef. VCircuitTimer LatchType ProtectionOscillatorMOS OutputMOS OutputMOS OutputMOS Input++1 210 912 1114 1316 15OUT2 V CCFB2E/A2E/A1 PWM1PWM2DTC2IN2 II2V REF DLY3 4 5 6 7 8C T R T IN1 II1 FB1 DTC1 OUT1 GND++Pin AssignmentDescriptionPin No. Pin Name Function22, 23~26, A0~A11 Address Multiplexed pins for row and column address.29~35 Row address: A0~A11. Column address: A0~A8.20, 21 BS0, Bank Select Select bank to activate during row address latch time, or bank toBS1 read/write during address latch time.2, 4, 5, 7, 8, DQ0~ Data Input/Output Multiplexed pins for data output and input.10,11, 13, 42, DQ1544,45, 47, 48,50, 51, 5319 CS# Chip Select Disable or enable the command decoder. When command decoder isdisabled, new command is ignored and previous operation continues.18 RAS# Row Address Strobe Command input. When sampled at the rising edge of the clock,RAS#, CAS# and WE# define the operation to be executed.17 CAS# Column Address Strobe Referred to RAS#16 WE# Write Enable Referred to RAS#15, 39 UDQM/ input/output mask The output buffer is placed at Hi-A (with latency of 2) when DQM isLDQM sampled high in read cycle. In write cycle, sampling DQM high willblock the write operation with zero latency.38 CLK Clock Inputs System clock used to sample inputs on the rising edge of clock.37 CKE Clock Enable CKE controls the clock activation and deactivation. When CKE is low,Power Down mode, Suspend mode, or Self Refresh mode is entered.1, 14, 27 Vcc Power (+3.3V) Power for input buffers and logic circuit inside DRAM.28, 41, 54 Vss Ground Ground for input buffers and logic circuit inside DRAM.3, 9, 43, 49 VccQ Power (+3.3V) for I/O buffer Separated power from Vcc, used for output buffers to improve noise.6, 12, 46, 52 VssQ Ground for I/O buffer Separated ground from Vss, used for output buffers to improve noise.36, 40 NC No Connection No Connection