SMCS332SpWUser ManualEADS Astrium GmbH, ASE2Doc No: SMCS_ASTD_UM_100Issue: 1.4Updated: 9-Sep-2006Page: 64 of 131– All Rights Reserved – Copyright per DIN 34 –7 Signal DescriptionThe Figure below shows the SMCS332SpW embedded in a typical module environment:SELECT AOE AWE ADATA AADDR ASELECT BOE BWE BDATA BADDR BDual PortCommunicationMemory BANK 0HOSTBIGEBOOTLINKRESETCLKCLK10SPACEWIRE LINK 1SPACEWIRE LINK 2SPACEWIRE LINK 34445TIME_CODE_SYNCJTAGHINTRHSELHRDHWRHACKHDATAHADRSMCSADRSMCSIDINTERRUPT INCHIP SELECTSREADWRITEWAIT/ACKDATAADDRESSCMCS1CMRDCMWRCMDATACMADRCMCS0PLLOUTCOCICOCOCAMSELECT AOE AWE ADATA AADDR ASELECT BOE BWE BDATA BADDR BDual PortCommunicationMemory BANK 1CPURSES4483232164VCCGNDIDProcessorSMCS332SpWThis section describes the pins of the SMCS. Groups of pins represent busses where the highest number is the MSB.O = Output; I = Input; Z = High ImpedanceO/Z = if using a configuration with two SMCS332SpWs these signals can directly be connected together (WIROR)(*) = active low signalSignal Name Type Function max. outputcurrent [mA]load [pF]HSEL* I Select host interfaceHRD* I host interface read strobeHWR* I host interface write strobeHADR(7:0) I SMCS register address lines. This address lines will beused to access (address) the SMCS registers.HDATA(31:0) I/O/Z SMCS data 3 50HACK O/Z host acknowledge. SMCS deasserts this output to add waitstates to a SMCS access. After SMCS is ready this outputwill be asserted.3 50HINTR* O host interrupt request line 3 50SMCSADR(3:0) I SMCS Address. The binary value of this lines will becompared with the value of the SMCS ID lines.SMCSID(3:0) I SMCS ID lines: offers possibility to use sixteen SMCSwithin one HSEL*HOSTBIGE I 0: host I/F Little Endian
