ESMT M12L16161AElite Semiconductor Memory Technology Inc. Publication Date : May. 2005Revision : 2.4 2/30SDRAM 512K x 16Bit x 2BanksSynchronous DRAMFEATURESz JEDEC standard 3.3V power supplyz LVTTL compatible with multiplexed addressz Dual banks operationz MRS cycle with address key programs- CAS Latency (2 & 3 )- Burst Length (1, 2, 4, 8 & full page)- Burst Type (Sequential & Interleave)z All inputs are sampled at the positive going edge of thesystem clockz Burst Read Single-bit Write operationz DQM for maskingz Auto & self refreshz 32ms refresh period (2K cycle)GENERAL DESCRIPTIONThe M12L16161A is 16,777,216 bits synchronous highdata rate Dynamic RAM organized as 2 x 524,288 words by16 bits, fabricated with high performance CMOS technology.Synchronous design allows precise cycle control with theuse of system clock I/O transactions are possible on everyclock cycle. Range of operating frequencies, programmableburst length and programmable latencies allow the samedevice to be useful for a variety of high bandwidth, highperformance memory system applications.ORDERING INFORMATIONPart NO. MAX Freq. PACKAGE COMMENTSM12L16161A-5TG 200MHz TSOP(II) Pb-freeM12L16161A-7TG 143MHz TSOP(II) Pb-freeM12L16161A-7BG 143MHz VFBGA Pb-freePIN CONFIGURATION (TOP VIEW)V DDDQ0DQ1V SSQDQ2DQ3V DDQDQ4DQ5V SSQDQ6DQ7V DDQLDQMWECASRASCSBAA10/APA0A1A2A3V DD1234567891011121314151617181920212223242550494847464544434241403938373635343332313029282726VSSDQ15DQ14VSSQDQ13DQ12VDDQDQ11DQ10VSSQDQ9DQ8VDDQN.C/RFUUDQMCLKCKEN.CA9A8A7A6A5A4VSS50PIN TSOP(II)(400mil x 825mil)(0.8 mm PIN PITCH)VSS DQ15DQ14 VSSQDQ13 VDDQDQ12 DQ11DQ10 VSSQDQ9 VDDQDQ8 NCNC NCNC UDQMNC CLKCKE NCA11 A9A8 A7A6 A5VSS A4DQ0 VDDVDDQ DQ1VSSQ DQ2DQ4 DQ3VDDQ DQ5VSSQ DQ6NC DQ7NC NCLDQM WECASNC CSNC NCA0 A10A2 A1A3 VDD1 2 3 4 5 6 7RASABCDEFGHJKLMNPR 60 Ball VFBGA(6.4x10.1mm)(0.65mm ball pitch)harman/kardonAVR 260/230 Service ManualPage 92 of 131