Harman Kardon AVR245 Service Manual

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Contents

Harman Kardon AVR245 Service Manual Manual pdf 209 page image

M24C64, M24C32DEVICE OPERATIONThe device supports the I 2 C protocol. This is sum-marized in Figure 5.. Any device that sends dataon to the bus is defined to be a transmitter, andany device that reads the data to be a receiver.The device that controls the data transfer is knownas the bus master, and the other as the slave de-vice. A data transfer can only be initiated by thebus master, which will also provide the serial clockfor synchronization. The M24Cxx device is alwaysa slave in all communication.Start ConditionStart is identified by a falling edge of Serial Data(SDA) while Serial Clock (SCL) is stable in theHigh state. A Start condition must precede anydata transfer command. The device continuouslymonitors (except during a Write cycle) Serial Data(SDA) and Serial Clock (SCL) for a Start condition,and will not respond unless one is given.Stop ConditionStop is identified by a rising edge of Serial Data(SDA) while Serial Clock (SCL) is stable and driv-en High. A Stop condition terminates communica-tion between the device and the bus master. ARead command that is followed by NoAck can befollowed by a Stop condition to force the deviceinto the Stand-by mode. A Stop condition at theend of a Write command triggers the internal Writecycle.Acknowledge Bit (ACK)The acknowledge bit is used to indicate a success-ful byte transfer. The bus transmitter, whether it bebus master or slave device, releases Serial Data(SDA) after sending eight bits of data. During the9th clock pulse period, the receiver pulls SerialData (SDA) Low to acknowledge the receipt of theeight data bits.Data InputDuring data input, the device samples Serial Data(SDA) on the rising edge of Serial Clock (SCL).For correct device operation, Serial Data (SDA)must be stable during the rising edge of SerialClock (SCL), and the Serial Data (SDA) signalmust changeonly when Serial Clock (SCL) is driv-en Low.Memory AddressingTo start communication between the bus masterand the slave device, the bus master must initiatea Start condition. Following this, the bus mastersends the Device Select Code, shown in Table 3.(on Serial Data (SDA), most significant bit first).The Device Select Code consists of a 4-bit DeviceType Identifier, and a 3-bit Chip Enable “Address”(E2, E1, E0). To address the memory array, the 4-bit Device Type Identifier is 1010b.Up to eight memory devices can be connected ona single I2 C bus. Each one is given a unique 3-bitcode on the Chip Enable (E0, E1, E2) inputs.When the Device Select Code is received, the de-vice only responds if the Chip Enable Address isthe same as the value on the Chip Enable (E0, E1,E2) inputs.The 8th bit is the Read/Write bit (RW). This bit isset to 1 for Read and 0 for Write operations.If a match occurs on the Device Select code, thecorresponding device gives an acknowledgmenton Serial Data (SDA) during the 9th bit time. If thedevice does not match the Device Select code, itdeselects itself from the bus, and goes into Stand-by mode.Table 6. Operating ModesNote: 1. X = V IH or V IL .Mode RW bit WC 1 Bytes Initial SequenceCurrent Address Read 1 X 1 START, Device Select, RW = 1Random Address Read 0 X 1 START, Device Select, RW = 0, Address1 X reSTART, Device Select, RW = 1Sequential Read 1 X ≥ 1 Similar to Current or Random Address ReadByte Write 0 V IL 1 START, Device Select, RW = 0Page Write 0 V IL ≤ 32 START, Device Select, RW = 0209AVR245 harman/kardon