Table 3. DMA I/O address map (continued)Address (hex) Description Bits Byte pointer008A Channel 7, page table address register 00 – 07008B Channel 5, page table address register 00 – 07008F Channel 4, page table address/refresh register 00 – 0700C0 Channel 4, memory address register 00 – 15 Yes00C2 Channel 4, transfer count register 00 – 15 Yes00C4 Channel 5, memory address register 00 – 15 Yes00C6 Channel 5, transfer count register 00 – 15 Yes00C8 Channel 6, memory address register 00 – 15 Yes00CA Channel 6, transfer count register 00 – 15 Yes00CC Channel 7, memory address register 00 – 15 Yes00CE Channel 7, transfer count register 00 – 15 Yes00D0 Channels 4–7, read status/write command register 00 – 0700D2 Channels 4–7, write request register 00 – 0200D4 Channels 4–7, write single mask register bit 00 – 0200D6 Channels 4–7, mode register (write) 00 – 0700D8 Channels 4–7, clear byte pointer (write) N/A00DA Channels 4–7, master clear (write)/temp (read) 00 – 0700DC Channels 4–7, clear mask register (write) 00 – 0300DE Channels 4–7, write all mask register bits 00 – 0300DF Channels 5–7, 8- or 16-bit mode select 00 – 0766 User Guide