Icom IC F110S Service Manual

Contents

Icom IC F110S Service Manual Manual pdf 7 page image

SECTION 4 CIRCUIT DESCRIPTION4 - 14-1 RECEIVER CIRCUITS4-1-1 ANTENNA SWITCHING CIRCUIT(MAIN UNIT)The antenna switching circuit functions as a low-pass filterwhile receiving and as resonator circuit while transmitting.This circuit does not allow transmit signals to enter thereceiver circuits.Received signals enter the antenna connector and passthrough the low-pass filter (L1–L3, C1, C2, C6–C8). The fil-tered signals are then applied to the RF circuit passedthrough the λ⁄4 type antenna switching circuit (D5, D6, D41,L6).4-1-2 RF CIRCUIT (MAIN UNIT)The RF circuit amplifies signals within the range of frequen-cy coverage and filters out-of-band signals.The signals from the antenna switching circuit pass throughthe two-stage tunable bandpass filters (D8, D4). The filteredsignals are amplified at the RF amplifier (Q2) and then enterother two-stage bandpass filters (D9, D10) to suppressunwanted signals. The filtered signals are applied to the 1stmixer circuit (Q3).The tunable bandpass filters (D4, D8–D10) employ varactordiodes to tune the center frequency of the RF passband forwide bandwidth receiving and good image response rejec-tion. These diodes are controlled by the CPU (FRONT unit;IC1) via the D/A converter (IC6).The gate control circuit reduces RF amplifier gain and atten-uates RF signal to keep the audio output at a constant level.The receiver gain is determined by the voltage on the “RSSI”line from the FM IF IC (IC1, pin 12). The gate control circuit(Q1) supplies control voltage to the RF amplifier (Q2) andsets the receiver gain.When receiving strong signals, the “RSSI” voltage increasesand the gate control voltage decreases. As the gate controlvoltage is used for the bias voltage of the RF amplifier (Q2),then the RF amplifier gain is decreased.4-1-3 1ST MIXER AND 1ST IF CIRCUITS(MAIN UNIT)The 1st mixer circuit converts the received signals to a fixedfrequency of the 1st IF signal with the PLL output frequency.By changing the PLL frequency, only the desired frequencywill pass through a MCF (Monolithic Crystal Filter; FI1) at thenext stage of the 1st mixer.The RF signals from the bandpass filter are applied to the1st mixer circuit (Q3). The applied signals are mixed with the1st LO signal coming from the RX VCO circuit (Q14) to pro-duce a 46.35 MHz 1st IF signal. The 1st IF signal passesthrough a MCF (Monolithic Crystal Filter; FI1) to suppressout-of-band signals. The filtered signal is amplified at the 1stIF amplifier (Q4) and applied to the 2nd IF circuit.4-1-4 2ND IF AND DEMODULATOR CIRCUITS(MAIN UNIT)The 2nd mixer circuit converts the 1st IF signal to a 2nd IFsignal. A double-conversion superheterodyne systemimproves the image rejection ratio and obtains stable receiv-er gain.The 1st IF signal from the 1st IF amplifier (Q4) is applied tothe 2nd mixer section of the FM IF IC (IC1, pin 16) and isthen mixed with the 2nd LO signal for conversion to a 450kHz 2nd IF signal.IC1 contains the 2nd mixer, limiter amplifier, quadraturedetector, active filter and noise amplifier circuits, etc. Atripled frequency from the PLL reference oscillator is usedfor the 2nd LO signal (45.9 MHz).The 2nd IF signal from the 2nd mixer (IC1, pin 3) passesthrough a ceramic filter (FI2) to remove unwanted hetero-dyned frequencies. It is then amplified at the limiter amplifi-er section (IC1, pin 5) and applied to the quadrature detec-tor section (IC1, pins 10, 11 and X1) to demodulate the 2ndIF signal into AF signals.The AF signals are output from pin 9 (IC1) and are thenapplied to the AF amplifier circuit.• 2nd IF and demodulator circuitsFI22nd IF filter450 kHz Q34IC4Limiteramp.Noiseamp.Noisecomp.FMdetectorActivefilterAF signals5VX1RSSI2ndMixerX215.3 MHz45.9 MHz1st IF from the IF amplifier (Q4)"NOIS" signal to the CPU"RSSI" signal to the CPU8 7 5BPFPLLIC3 2316131211109IC1TA31136FN"SQLIN" signalfrom the D/Aconverter IC (IC6).("DET" signal)