5 - 45-3 PLL CIRCUITS5-3-1 VOLTAGE CONTROLLED OSCILLATORS(VCOs; MAIN UNIT)VCO is an oscillator whose oscillating frequency is controlledby adding voltage (lock voltage).This transceiver has 2 VCOs RX VCO (Q17, D9, D11) andTX VCO (Q16, D10, D13). The RX VCO oscillates the 1st LOsignals, and the TX VCO oscillates the transmit signal.• RX VCOThe output signals are amplifi ed by the buffer amplifi ers (Q15,Q29), and applied to the 1st mixer (Q6) via TX/RX switches(D16 is OFF, D17 is ON) and LPF (L46, C396, C397), to bemixed with the received signals to produce the 46.35 MHz 1stIF signal.• TX VCOThe output signal is applied to the transmit amplifiers via thebuffer amplifi ers (Q15, Q29) and TX/RX switches (D16 is ON,D17 is OFF).A portion of each VCO output is applied to the PLL IC (IC2, pin8) via the buffer amplifi er (Q15), doubler (Q14) and BPF (L32,L34, C196, C197, C205).5-3-2 PLL IC (MAIN UNIT)The PLL circuit provides stable oscillation of the transmitfrequency and receive 1st LO frequency. The PLL outputfrequency is controlled by the divided ratio (N-data) from theCPU.The VCO output signal from the BPF (L32, L34, C196, C197,C205) is applied to the PLL IC (IC2, pin 8). The appliedsignal is divided at the prescaler and programmable counteraccording to the “SSO” signal from the CPU (IC22, pin 99).The divided signal is phase-compared with the referencefrequency signal from the reference frequency oscillator (X2),at the phase detector.The phase difference is output from pin 5 as a pulse typesignal after being passed through the internal charge pump.The output signal is converted into the DC voltage (lockvoltage) by passing through the loop filter (R94–R96, C16,C17, C146). The lock voltage is applied to the varactors (D9and D11 of RX VCO, D10 and D13 of TX VCO) and locked tokeep the VCO frequency constant.If the oscillated signal drifts, its phase changes from that ofthe reference frequency, causing a lock voltage change tocompensate for the drift in the VCO oscillating frequency.• PLL CIRCUITSLoopfilterModulation signalsfrom the D/A converter(IC12, pin10)RX VCOQ16, D10, D13D12Q17, D9, D11TX VCOPLL control signals from the CPU (IC22)PLL unlock signalto the CPU (IC22, pin 34)15.3 MHzreference frequency signalBufferBuffer×2to the transmit amplifiersto the1st IF circuitsD17D16BPFPLSTSSOSCK578191011PLL IC (IC2)Shift registerPrescalerPhasedetectorChargepump ProgrammabledividerReferencecounterQ15Q29Q14X2TCXO