Icom IC-F410 Service Manual

Also see for IC-F410: Instruction manual Instruction manual

Contents

Icom IC-F410 Service Manual Manual pdf 9 page image

4 - 34-2-3 DRIVE AMPLIFIER CIRCUIT (MAIN unit)The drive amplifier circuit amplifies the VCO oscillating sig-nal to the level needed at the power amplifier.The RF signal from the buffer amplifier (Q30) passesthrough the T/R switch (D18) and is amplified at the buffer(Q21, Q20) and drive (Q19) amplifiers. The amplified signalis applied to the power amplifier circuit.4-2-4 POWER AMPLIFIER CIRCUIT (MAIN unit)The power amplifier circuit amplifies the driver signal to anoutput power level.The RF signal from the drive amplifier (Q19) is applied to thepower module (IC5) to obtain 35 W (for IC-F420/F420S; 25W for IC-F410/F410S) of RF power.The amplified signal is passed through the antenna switch-ing circuit (D3), low-pass filter and APC detector, and is thenapplied to the antenna connector.Collector voltages for the driver (Q19) and control voltagefor the power amplifier (IC5, pin 2) come from the APC con-troller (Q17, Q18) to stabilize the output power. The transmitmute switch (Q16) controls the APC controller when transmitmute is necessary.4-2-5 APC CIRCUIT (MAIN unit)The APC circuit protects the power amplifier from a mis-matched output load and stabilizes the output power.The APC detector circuit (D1) detects forward signals andreflection signals. The combined voltage is at minimum levelwhen the antenna impedance is matched at 50 Ω and isincreased when it is mismatched.The detected voltage is applied to the inverse amplifier(IC4b, pin 6), and the power setting voltage (T4) is appliedto the other input (pin 5) for the reference. When antennaimpedance is mismatched, the detected voltage exceedsthe power setting voltage. The output voltage of the inverseamplifier (IC4b, pin 7) controls the input current of the powermodule (IC5) and drive amplifier (Q19) to reduce the outputpower via the APC controller (Q17, Q18).4-3 PLL CIRCUITS4-3-1 PLL CIRCUITA PLL circuit provides stable oscillation of the transmit fre-quency and receive 1st LO frequency. The PLL circuit con-sists of the PLL IC (IC2), loop filter and reference oscillatorcircuit and employs a pulse swallow counter.An oscillated signal from the VCO (Q23, Q25) passesthrough the buffer amplifiers (Q28, Q29), is applied to thePLL IC (IC10, pin 2) and is prescaled in the PLL IC based onthe divided ratio (N-data). The reference signal is generatedat the reference oscillator (X2) and is also applied to the PLLIC. The PLL IC detects the out-of-step phase using the ref-erence frequency and outputs it from pin 8. The output sig-nal is passed thorough the loop filter (Q34, R180, R181,C203, C231) and is then applied to the VCO circuit as thelock voltage.4-3-2 VCO CIRCUIT (MAIN unit)The VCO circuit contains a separate RX VCO (Q23, D20,D34) and TX VCO (Q25, D22, D33). The oscillated signal isamplified at the buffer amplifiers (Q28, Q29) and is thenapplied to the T/R switching circuit (D18, D19). The Rx sig-nal is applied to the 1st mixer circuit (Q3) and the Tx signalto the driver (Q19) via the buffer amplifers (Q21, Q20).A portion of the signal from Q28 is amplified at the bufferamplifier (Q29) and is then fed back to the PLL IC (IC10,pin 2).• PLL circuitShift register×3PrescalerPhasedetectorLoopfilterProgrammablecounterProgrammabledividerX115.3 MHz45.9 MHz signalto the FM IF IC15Q23, D20, D34RX VCOTX VCOBufferBufferBufferQ30Q29Q28345PLSTIC10 (PLL IC)SCKSOto transmitter circuitto 1st mixer circuitD19D18178 2Q25, D22, D33