5 - 4LoopfilterX115.3 MHzQ2, D5, D6RX VCO2Q1, D1, D2RX VCO1TX VCOQ3, D9, D10PLL control signals from the CPU (IC18)PLL unlock signalto the CPU (IC18, pin 73)15.3 MHzreference frequency signal• PLL CIRCUITBufferQ4BufferQ6BufferQ5to transmitter circuitto 1st mixer circuitD15D14BPFPLSTSSDSCK411610141516PLL IC (IC1)Shift registerPrescalerPhasedetectorDivideratioadjustmentChargepumpProgrammabledividerReferencedividerCPU5Vregurator+5VreguratorVREFreguratorS5VreguratorT5VreguratorR5VreguratorPower switchQ30, Q31Q12, Q13, Q8IC9IC6Q14Q15Q16HVVCCCPU5VCPU+5VVREFS5V “S5C”Voltage lineControl signal8282627“T5C”“R5C”T5VReceiver circuitsAttached optional units,AF amplifier controller(FRONT UNIT; Q501, Q502, D508),etc.CPU (IC18),EEPROM (IC19),etc.PLL IC (IC1),Base band IC (IC5),etc.PLL IC (IC1)Transmitter circuitsR5V(IC18)Attached optional units,D/A converters,etc.Battery packThe buffer-amplified VCO output signals from the tunable BPF(L601−L603, C601−C607) are applied to the PLL IC (IC1,pin 6). The applied signals are divided at the prescaler andprogrammable counter according to the “SSD” signal from theCPU (IC18, pin 10). The divided signal is phase-compared withthe reference frequency signal from the reference frequencyoscillator (X1), at the phase detector.The phase difference is output from pin 4 as a pulse type signalafter being passed through the internal charge pump. The outputsignal is converted into the DC voltage (lock voltage) by passingthrough the loop filter (R7, R8, R12, C14, C16, C19). The lockvoltage is applied to the varacter diodes (D1 and D2 of RXVCO1, D5 and D6 of RX VCO2, D9 and D10 of TX VCO) andlocked to keep the VCO frequency constant.If the oscillated signal drifts, its phase changes from that ofthe reference frequency, causing a lock voltage change tocompensate for the drift in the VCO oscillating frequency.5-4 POWER SUPPLY CIRCUITSVoltage from the attached battery pack is routed to whole of the circuit in the transceiver via switches and regulators.