Icom IC-F80DS Service Manual

Also see for IC-F80DS: Operating guide Instruction manual Instruction manual Instruction manual Service manual addendum

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Icom IC-F80DS Service Manual Manual pdf 10 page image

4-3 PLL CIRCUITS4-3-1 PLL CIRCUIT (MAIN UNIT)The PLL circuit provides stable oscillation of the transmitfrequency and receive 1st LO frequency. The PLL circuitcompares the phase of the divided VCO frequency with thereference frequency. The PLL output frequency is controlledby the divided ratio (N-data) of the programmable divider.The PLL circuit contains the two RX VCOs (Q600, D604,D605 for 400–434 MHz, Q601, D606, D607 for 435–470MHz) and one TX VCO (Q602, D608, D609). The oscillatedsignal is amplified at the buffer amplifiers (Q605, Q606,Q608) and applied to the PLL IC (IC1, pin 6) after beingpassed through the LPF (L2, L3, C22, C25, C27, C28, C37).The applied signal is divided at the prescaler and program-mable divider section by the N-data ratio from the CPU(IC307). The divided signal is phase-compared with the devidedreference frequency at the phase detector. The phase dif-ference is output from pin 4 as a pulse signal after beingpassed through the charge pump section. The output signalis passed through the loop filter (R16, R17, C17, C24, C29,C31) to converted into the DC voltage, and is then appliedto the VCO circuits as the lock voltage.If the oscillated signal drifts, its phase changes from that ofthe reference frequency, causing a lock voltage change tocompensate for the drift in the oscillated frequency.4-3-2 VCO CIRCUITS (MAIN UNIT)The VCO circuits contain separate two RX VCOs (Q600, D604,D605 for 400–434 MHz, Q601, D606, D607 for 435–470MHz) and one TX VCO (Q602, D608, D609). The oscillatedsignal is amplified at the buffer amplifiers (Q605, Q606,Q609) and is then applied to the TX/RX switch (D200,D501). Then the receive 1st LO (RX) signal is applied to the1st mixer (IC500, L503, L504, L506), and the transmit (TX)signal is applied to the buffer amplifier (Q200).A portion of the signal from the buffer amplifier (Q605,Q606) is fed back to the PLL IC (IC1, pin 6) as the compari-son signal via the buffer amplifier (Q608) and the LPF (L2,L3, C22, C25, C27, C28, C37).4 - 4LoopfilterPLSTSSOSCK4Q601, D606, D607RX VCO (435–470 MHz)Q600, D604, D605RX VCO (400–434 MHz)TX VCOQ602, D608, 609610141516 PLL control signals from CPU (IC307)15.3 MHz reference signalfrom reference frequency osciilator (X1)IC1 LMX2352TM• PLL CIRCUITShift registerPrescalerPhasedetectorDividedratioadjustmentChargepump ProgrammabledividerReferencedividerBufferQ605,Q606BufferQ609BufferQ608to transmitter circuitto 1st mixer circuitD501D200LPFLINE DESCRIPTIONVCC The voltage from the attached battery pack passedthrough the power switch (Q309).CPU5V Common 5 V for the CPU (IC307) converted from theVCC line at the CPU5V regulator (IC311).5V Common 5 V line converted from the VCC line at the+5V regulator (Q307, Q308).T5V5 V for the transmit circuits regulated from the 5V lineby the T5V switch (Q305).The switch is controlled by the "T5C" signal from theCPU (IC307, pin 16).S5V5 V for the power save line regulated from the 5V lineby the S5V switch (Q304).The switch is controlled by the "S5C" signal from theCPU (IC307, pin 27).R5V5 V for the receive circuits regulated from the 5V lineby the R5V switch (Q306).The regulator is controlled by the "R5C" signal fromthe CPU (IC307, pin 26).4-4 POWER SUPPLY CIRCUITS4-4-1 VOLTAGE LINES (MAIN UNIT)LINE DESCRIPTIONDVDD3.3V3.3 V for the CPU (IC12; DSP UNIT), DSP IC (IC7)and EEPROM (IC17) regulated from the 5V line by the+3VC regulator (IC1).CVDD1.5V 1.5 V for the DSP IC (IC7) converted from the +5Vline at the +1.5VA regulator (IC2).+3VD 3.3 V for the A/D converter (IC8) and LINER CODECIC (IC9) from the 5V line at the +3VD regulator (IC3).4-4-2 VOLTAGE LINES (DSP UNIT)