Icom IC-M422 Service Manual

Also see for IC-M422: Instruction manual Service manual

Contents

4 - 34-3 PLL CIRCUITS4-3-1 VCO CIRCUITThe VCO circuit (Q4, Q5, D3, D4) directly generates both of the1st LO frequency for receiving (134.35–141.575 MHz) and thetransmit frequency (156.025–157.425 MHz).While receiving, the VCO output signal (1st LO signal) is am-plified at the buffer amplifiers (Q6, Q7) and passed throughthe TX/RX switch (D8), then applied to the 1st mixer (Q22).While transmitting, the VCO output signal (transmit signal)is amplified at the buffer amplifiers (Q6, Q7) and passedthrough the TX/RX switch (D7), then applied to the pre-driver(Q10).A portion of the VCO output signal from the buffer amplifier(Q6) is fed back to the PLL IC (IC1, pin 2) as the comparisonsignal via the buffer amplifier (Q3) and the LPF (L2, C34,C35).4-3-2 PLL CIRCUITThe PLL circuit provides stable oscillation of the transmitfrequency and receive 1st LO frequency. The PLL circuitcompares the phase of the divided VCO frequency with thereference frequency. The PLL output frequency is controlledby the divided ratio of the programmable divider.The buffer amplified signals are applied to the PLL IC (IC1,pin 2) via the LPF (L2, C34, C35). The applied signals aredivided at the prescaler and programmable counter sectionaccording to the “PDATA” from the CPU (LOGIC BOARD; IC1pin 8). The divided signal is phase-compared with the referencefrequency at the phase detector.The phase difference is output from pin 8 as a pulse typesignal after being passed through the charge pump section.The output signal is passed through the loop filter (R7–R9,R41, C4, C5, C43, C44) to be converted into the DC voltage,and is then applied to the VCO circuits as the lock voltage.If the oscillated signal drifts, its phase changes from that ofthe reference frequency, causing a lock voltage change tocompensate for the drift in the oscillated frequency.4-4 DSC CIRCUITS• DECODINGA portion of the demodulated AF signals from the FM IF IC(IC2, pin 9) are passed through the LPF (Q38) to filter DSCsignal. The filtered DSC signal is applied to the DSC de-coder (IC15, pin 2). The decoded DSC signal is output frompin7, and then applied to the CPU (LOGIC BOARD; IC1, pin14). Then the CPU controls the transceiver according to theDSC content.• ENCODINGThe DSC signals (FSK) are generated by the CPU (LOGICBOARD; IC1) and output from pins 141. The DSC signalsare applied to the buffer amplifier (LOGIC BOARD; IC5,pin 3). The buffer amplified DSC signals are output frompin 1, and passed through the LPF (IC8, pins 5, 7), andapplied to the modulation circuit (D2) via the deviationadjustment pot (R327) to modulate the VCO oscillatingsignal.4-5 PUBLIC ADDRESS (PA) CIRCUITThe Public Address (PA) circuit power amplifies the audiosignals from the microphone. The power amplified MIC sig-nals are output to the connected external speaker or hailer.The MIC signals from the microphone (HM-150B/SW oroptional HM-157) are passed through the AF mute circuit(IC5, pins 10, 11), and applied to the microphone amplifier(IC8, pin 2). The amplified MIC signals are output from pin 1,and applied to the electric volume controller (IC13, pin 1) viathe AF mute circuit (IC5, pins 8, 9). The volume controlledMIC signals are then passed through the AF mute circuit(Q65), and applied to the AF power amplifier (IC14, pin 1) tobe amplified to obtain 5 W (min.) of AF output power.The power amplified AF signals are output from pin 4, andapplied to the connected external speaker or hailer.DATA interfacePrescalerPhasedetectorLoopfilterReferencecounterProgrammablecounterChargepumpBufferQ6BufferQ7BufferQ3 to the TX/RX switch (D7, D8)Q4, Q5, D3, D4VCOLPFto the FM IF IC (IC2, pin 2)387 2171516PSTBUNLK• PLL CIRCUITSPCKPDATAX145S5VIC1μPD3140GS