Icom IC-M700PRO Servise Manual

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Icom IC-M700PRO Servise Manual Manual pdf 10 page image

3 - 53-2-8 APC CIRCUITThe APC (Auto Power Control) circuit protects the poweramplifiers on the PA unit from high SWR and excessivecurrent.(1) SWR APC (FILTER BOARD AND MAIN UNIT)The reflected wave signal appears and increases on theantenna connector. When the antenna is mismatched,D4310 of the power detector circuit (FILTER board; D4309,D4310, L4341) detects the signal and applies it to the APCamplifier (MAIN unit; Q23). The amplified signal decreasesthe bias voltage of the RF ALC amplifier to reduce the out-put power.(2) CURRENT APC (PA150W BOARD AND MAIN UNIT)The power transistor current is detected from the differ-ent voltages between both terminals of a 0.012 Ω resistor(R4026) on the PA150W board. The detected voltage isapplied to the differential amplifier (IC4002b). When the cur-rent of the final transistors is more than 30 A, the detectedvoltage is applied to the APC amplifier controller (MAINunit; Q111) to reduce the gate-2 voltage of the IF amplifier(MAIN unit; Q2) and thus reduce the output power.3-2-9 TEMPERATURE DETECTION(PA150W BOARD)Thermal switches (S4001, S4002) protect the final transis-tors from excessive temperatures. When the temperature ofthe final transistors exceeds 50˚C (122˚F), S4002 is turnedON to start the cooling fan. When the temperature of thefinal transistors exceeds 110˚C (230˚F), S4001 is turnedON to control the “POC2” line and sets the power to 60 W.3-2-10 RF METER CIRCUIT (MAIN UNIT)The output of the ALC amplifier (IC16a) is applied to theCPU (pin 31) to indicate the transmit power level on thedisplay.For antenna current meter indication, the “ANTC” signalfrom an optional AT-130E is applied to the CPU (pin 32).3-3 PLL CIRCUIT3-3-1 GENERALThe PLL unit generates a 1st LO frequency (69.5115–99.0114 MHz), 2nd LO frequency (60 MHz) and a BFO fre-quency (9.0106–9.013 MHz) for the MAIN unit. The 1st LOPLL adopts a mixerless dual loop PLL system. The BFOuses a DDS and a 2nd LO as a fixed frequency double thatthe crystal oscillator.3-3-2 1ST LO PLL (PLL UNIT)The 1st LO PLL contains a main loop and reference loopas a dual loop system. The reference loop generates a10.65 to 10.75 MHz frequency using a DDS circuit, and themain loop generates a 69.5115 to 99.0114 MHz frequencyusing the reference loop frequency.(1) REFERENCE LOOP PLLThe oscillated signal at the reference VCO (Q3005, D3003)is amplified at the buffer amplifiers (Q3006, Q3011) and isthen applied to the DDS IC (IC3001, pin 46). The signal isthen divided and detected on phase with the DDS gener-ated frequency.The detected signal output from IC3001 (pin 56) is convert-ed into a DC voltage (lock voltage) at the loop filter (R3018,R3019, C3044) and then fed back to the varactor diode(D3003) in the VCO circuit.(2) MAIN LOOP PLLThe oscillated signal at the main loop VCO (Q3003, D3004)is amplified at the buffer amplifiers (Q3004, Q3008), and isthen applied to the PLL IC (IC3005, pin 14). The signal isthen divided and detected on phase with the reference loopoutput frequency.The detected signal output from IC3005 (pins 3009, 3010)is converted into a DC voltage (lock voltage) at the loopfilter and then fed back to the varactor diode (D3004) in theVCO circuit.The oscillated signal is amplified at the buffer amplifiers(Q3004, Q3021, Q3024) and then applied to the MAIN unitas a 1st LO signal.PLL IC (IC3005)ProgrammabledividerProgrammabledividerProgrammabledividerProgrammabledividerPhasePhasedetectordetectorDDSD/AconvertorconvertorLoop filterLoop filterQ3011Reference loop VCOQ3005/D3003Q3008Main loop VCOQ3004Q3003/D300410.65–10.75 MHzQ3006DDSIC3002Q3002DoublerD/AReference OSC (X3001; 30.0 MHz)Q3021 Q30241LO(69.5115–99.0114 MHz)2LO(60.0 MHz)BFO(9.0106–9.013 MHz)DDS IC(IC3001)• PLL CIRCUIT