Icom IC-PCR1500 Service Manual

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Icom IC-PCR1500 Service Manual Manual pdf 15 page image

pulse-type signal at the noise detector section, and outputfrom pin 13 as the “NOIS” signal. The “NOIS” signal isapplied to the CPU (IC18, pin 16). And the CPU outputscontrol signals “LSTB,” “VDAT,” “VCK” from pins 61, 57, 58,to the expander (IC34) according to the “NOIS” signal level.Then the expander outputs “SPPWR” signal from pin 7 totoggle the AF+8V regulator (Q5, Q8) ON and OFF.The expander also outputs “SPMUTE” signal to the speakerswitch (Q12, D28) at the same time, to disconnect the AF line.• TONE SQUELCH (LOGIC UNIT)The tone squelch detects the tone (CTCSS/DTCS) signalin the demodulated AF signals, and opens the squelch onlywhen the matched sub-audible tone frequency is detected inthe received signal.While the tone squelch is in use, and the received signalcontains no sub-audible tone or mismatched tone frequency,the tone squelch mutes the AF signals even if the noisesquelch is open.A portion of the demodulated AF signals from the IF IC(MAIN-A/B; IC24, pin 9) are passed though the tone filter(IC21/IC2021, pins 5, 7) to suppress unwanted voice signals.The filtered tone signals are applied to the CPU (IC18, pin93/85).The CPU decodes the CTCSS/DTCS signal, and outputscontrol signals “LSTB,” “VDAT,” “VCK” from pins 61, 57, 58, tothe expander (IC34) according to the applied CTCSS/DTCSsignal. Then the expander outputs “SPPWR” signal from pin7 to toggle the AF+8V regulator (Q5, Q8) ON and OFF.The expander also outputs “SPMUTE” signal to the speakerswitch (Q12, D28) at the same time, to disconnect the AF line.4-1-8 BANDSCOPE CIRCUITS* (MAIN-A UNIT)A portion of the 2nd IF signal from the 2nd mixer (IC19, pin5) is applied to the IF IC (IC20, pin 16) via the 2nd IF filter(FI2). The 2nd IF signal is converted into the 3rd IF signal bybeing mixed with 3rd LO signal from the DDS circuits, at the3rd mixer in the IF IC (IC20).䇭The converted 3rd IF signalis output from pin 3 and passed through the 3rd IF filter FI4.The filtered signal is amplified at the limiter amplifier in theIC to produce the RSSI signal which corresponding to thereceived signal level.The RSSI signal “SCAD” is output from pin 12, and appliedto the CPU (IC18, pin 89). The CPU converts the RSSI signalinto the digital signal, and outputs to connected PC via USBHUB (IC32, pins 19, 20 and 2, 3) to indicate the receivedsignal level for bandscope function on the PC screen.4-2 PLL CIRCUITS4-2-1 VCO CIRCUITS (MAIN-A/B UNITS)DOWN CONVERTER VCO*The down converter VCO (Q19, D43) generates the 1001MHz LO signals for down conversion.The VCO output signals are buffer amplified by Q13,and applied to the mixer (IC6, pin 3) for frequency down-conversion, via the band switches (D11, D12, D21, D22).When the recceiving 2000 MHz and above, the VCO outputsare doubled by being passed through the HPF (L23, C61,C69, C75), and applied to the mixer (IC6, pin 3) as the 2002MHz LO signals via the band switches (D12, D22).• 1st VCO’sThe 1st VCO is composed by two VCO’s; as the 1st LOsignal generator for 0.01–483.29 MHz and 483.3–3300 MHzreception range.[When receiving 0.01–265.6999 MHz signals]-1st VCO 1 (Q28, D53)-Generates 532.4–749.95 MHz LO signals. The VCO outputsignal is buffer-amplified by Q27. The buffer amplified signalsare passed through the LO siwtch (D58) and buffer amplifier(IC15, pins 1, 4).-1st VCO 2 (Q30, D54)-Generates 750–1066.65 MHz LO signals. The VCO outputsignal is buffer-amplified by Q29. The buffer amplified signalsare passed through the LO siwtch (D59) and buffer amplifier(IC15, pins 1, 4).The buffer amplified VCO output signals from pin 4 of IC15are passed through the attenuator (R137, R138, R152), LOswitch (D57) and another attenuator (R153, R154, R156),and applied to the 1 / 2 frequency divider (IC11, pin 2). Thedivided LO signals are buffer-amplified by Q34, and thenpassed through the HPF (L113, C316, C321), LPF (L115,L118, C326, C322), LO switch (D85) and attenuator (R214,R217, R226), before being applied to the 1st mixer (IC14,pins 1, 6).[When receiving 266.7–33000 MHz signals]-1st VCO 1 (Q28, D53)-Generates 532.4–749.95 MHz LO signals. The VCO outputsignal is buffer-amplified by Q27. The buffer amplified signalsare passed through the LO siwtch (D58) and buffer amplifier(IC15, pins 1, 4).-1st VCO 2 (Q30, D54)-Generates 750–1066.65 MHz LO signals. The VCO outputsignal is buffer-amplified by Q29. The buffer amplified signalsare passed through the LO siwtch (D59) and buffer amplifier(IC15, pins 1, 4).The buffer amplified VCO output signals from pin 4 of IC15are passed through the attenuator (R137, R138, R152) andLO switches (D60, D84) and BPF (L107, L108, C276, C278,C288, C292, C298), before being applied to the 1st mixer(IC14, pins 1, 6).• 2nd VCOThe 2nd VCO (Q47, D62, D63) generates the LO signalsfor producing 2nd IF signal. The oscillated signals are bufferamplified by Q50, and applied to the 2nd mixer (IC19, pin 1)via LPF (L158, C456, C459, C462) and attenuator (R276).4-2-2 PLL CIRCUITS (MAIN-A/B UNIT)The PLL circuits provide stable oscillation of the receive LOfrequencies. The PLL circuit compares the phase of thedivided VCO frequency with the reference frequency. The PLLoutput frequency is controlled by the divided ratio (N-data)from the CPU.• DOWN CONVERTER PLL*A portion of the VCO output signals are amplified at thebuffer amplifier (Q14) and then applied to the PLL IC (IC4,pin 8). The applied signals are divided at the prescaler andprogrammable counter according to the N-data “DAT1” fromthe expnader (IC3, pin 2) controlled by the CPU (LOGICUNIT; IC18). The divided signal is phase compared with thereference frequency from the reference amplifier (Q5) at thephase comparator.4 - 4*MAIN-A UNIT only