Icom IC-V8 Service Manual

Also see for IC-V8: Instruction manual Instruction manual Service manual Instruction manual

Contents

4 - 34-3 PLL CIRCUITSA PLL circuit provides stable oscillation of the transmit fre-quency and receive 1st LO frequency. The PLL output com-pares the phase of the divided VCO frequency to the refer-ence frequency. The PLL output frequency is controlled bythe divided ratio (N-data) of a programmable divider.The PLL circuit contains the VCO circuit (Q50, D38). Theoscillated signal is amplified at the LO (Q6) and buffer (Q5)amplifiers and then applied to the PLL IC (IC1, pin 6).The PLL IC contains a prescaler, programmable counter,programmable divider, phase detector, charge pump, etc.The entered signal is divided at the prescaler and program-mable counter section by the N-data ratio from the CPU.The divided signal is detected on phase at the phase detec-tor using the reference frequency.If the oscillated signal drifts, its phase changes from the ref-erence frequency, causing a lock voltage change to com-pensate for the drift in the oscillated frequency.A portion of the VCO circuit is amplified at the LO (Q6) andbuffer (Q4) amplifiers and is then applied to the receive 1stmixer or transmit pre-drive amplifier circuit via the TX/RXswtiching diode (D3, D4).4-4 OTHER CIRCUITS4-4-1 TONE SQUELCH CIRCUITA portion of the detected audio signals from the “DET” lineare passed through the tone filter (Q53). The filtered signalis then applied to the CPU (IC1, pin 94) via the “CTCIN” sig-nal, and is compared with the programmed tone signal. TheCPU (IC1) outputs control signals as “CTCC” signal to theAF mute and AF regulator circuits to open the squelch whena matched tone signal is received.The programmed subaudible tone signal is output from theCPU (IC1, pin 91) directly when transmitting with a tone.Shift registerPrescalerPhasedetectorLoopfilterProgrammablecounterProgrammabledividerX121.25 MHz21.25 MHz signalto the FM IF IC"DEV" signal from the D/Aconvertor (IC10, pin 22)when transmitting1Q50, D38VCO circuit LOamp. BufferBuffer234PLCKSOPLSTto transmitter circuitto 1st mixer circuitD4D3169 6Q6 Q4Q5IC1 LV2105VVCO SHIFTR5Q51, D37• PLL CIRCUITLINEVCCCPU5SW5VVCO5PS5R5T5DESCRIPTIONThe voltage from the attached battery pack.Common 5 V converted from the VCC line by theCPU5 regulator (IC12). The output voltage isapplied to the CPU (IC8), EEPROM (IC7) andreset IC (IC11).Common 5 V converted from the VCC line by theSW5 regulator circuit (Q55, Q57, D39). The out-put voltage is applied to the T5, R5, PS5 andVCO5 regulator circuits, D/A convertor (IC10, pin16), etc.Common 5 V converted from the SW5V line bythe VCO5 regulator circuit (Q11) using the LO(Q6) and buffer (Q4, Q5) amplifiers. The VCO5regulator circuit is controlled by the PSVCO linefrom the CPU (IC8, pin 62).Common 5 V converted from the SW5V line bythe PS5 regulator circuit (Q54) using the analogswitch (IC14, pin 14) and APC controller (Q37).The PS5 regulator circuit is controlled by thePS5C line from the CPU (IC8, pin 63).5 V for receiver circuits converted from theSW5V line by the R5 regulator circuit (Q21)using the 2nd IF IC (IC2, pin 4), RF (Q12) and IF(Q14) amplifiers, etc. The R5 regulator circuit iscontrolled by the R5C line from the CPU (IC8,pin 53).5 V for the transmitter circuit converted from theSW5V line by the T5 regulator circuit (Q22) usingthe pre-drive amplifier (Q3). The T5 regulator cir-cuit is controlled by the T5C line from the CPU(IC8, pin 54).4-5 POWER SUPPLY CIRCUITSVOLTAGE LINE