Icom IC-V82 Service Manual

Also see for IC-V82: Instruction manual Addendum Specifications Instruction manual Instruction manual

Contents

4 - 6LinearCODECBufferIC253BBufferIC251ABufferIC251BIC50IC151Q305, Q306IC351-"232C_RX" signalto the J301, pin 25-"232C_TX" signalto the J301, pin 26-"TXD_2" signal tothe J301, pin 16-"RXD_2" signal tothe J301, pin 17"DAFOUT" signal tothe J301, pin 22"DMOD" signalto the J301, pin 3"FMDET" signalfrom the J301, pin 23"AMODIN" signalfrom the J301, pin 4IC204 IC252DSPCODECCPUCODEC ModemRS-232CLevelconverter• UT-118 BLOCK DIAGRAM4-7 UT-118 CIRCUIT DESCRIPTION4-7-1 RECEIVER CIRCUITThe detected digital signals “FMDET” from the connectedtransceiver via the J301 (pin 22) are amplified at the bufferamplifier (IC251, pin 2). The amplified signals are appliedto the GMSK modem circuit (IC252, pin 11), and are thenapplied to the CPU (IC204) as clock synchronizer digitalsignal. The digital signals from the CPU are applied to theAMBE voice CODEC IC (IC151) to press code extension,and are then applied to the linear CODEC IC (IC50) as32 bits digital voice data. The applied digital signals areconverted to the analog AF signals at the D/A convertersection (IC50), and are then applied to the connectedtransceiver via the J301 (pin 21) as “DAFOUT” signal.4-7-2 TRANSMITTER CIRCUITThe analog AF signals “AMODIN” from the connectedtransceiver via the J301 (pin 4) are amplified at the bufferamplifier (IC251, pin 6). The amplified signals are appliedto the linear CODEC IC (IC50, pin 5) to convert 32 bitsdigital voice data at the A/D converter section via the “ADIN”line. The digital signals are applied to the AMBE voiceCODEC IC (IC151) to process code compression, and arethen applied to the CPU (IC204). The digital signals fromthe CPU convert to the GMSK base band signal at theGMSK modem (IC252), and are then amplified at the bufferamplifier (IC253, pin 5). The amplified signals are applied tothe connected transceiver via the J301 (pin 3).4-7-3 RESET CIRCUITThe UT-118 has the reset IC (IC203). The reset IC outputs"RES" signal to the CPU (IC204, pin 7) when more than 2.8 Vof voltage is applied to the “VDD” port (pin 2).4-7-4 RS-232C CIRCUITIC351 is a RS-232C compatible serial interface IC whichconverts data between the CPU and the external equipment(ex. Personal Computer).4-7-5 LEVEL CONVERTER CIRCUITThe level converter circuit (Q305 and Q306) convertscommunication data level between the CPU (IC204) and theconnected transceiver’s CPU.Q301, Q302 and Q303 convert control signals level betweenthe UT-118 and the IC-V82.4-8 UT-118 POWER SUPPLY CIRCUITS4-8-1 VOLTAGE LINES4-9 UT-118 PORT ALLOCATIONS4-9-1 MODEM IC (IC252)LINE DESCRIPTION5V5 V from the connected transceiver via the J301 (pin29). The 5V line is controlled by the +5 V controlcircuit (Q50 and Q51). The circuit is controlled bythe “PSAVE” signal from the CPU (IC204, pin 58and 59).3.3VCommon 3.3 V converted from the 5V line by the3.3V regulator circuit (IC1). One of the 3.3 V line iscontrolled by the +3V control circuit (Q400 andQ401). The circuit is controlled by the “PSAVE”signal from the CPU (IC204, pin 58 and 59).3.2VCommon 3.2 V converted from the 4.5–8 V lineby the 3.2V regulator circuit (IC2). The circuit iscontrolled by the “APWR” signal from the CPU(IC204, pin 16).PINNUMBERPORTNAME DESCRIPTION2 MCLK Outputs 2.4576 MHz clock signal tothe CPU (IC151, pin 39).7 ACQ Outputs the PLL bandwidth controlsignal while receiving.19 TXDT Outputs transmitting data signal tothe CPU (IC204, pin 54).20 RXDT Input port for receiving data signalfrom the CPU (IC204, pin 53).21 RXCK Input port for receive clock signalfrom the CPU (IC204, pin 52).22 TXCK Outputs transmit clock signal to theCPU (IC204, pin 51).