4 - 74-5 PORT ALLOCATIONS4-5-1 CPU (LOGIC-1 UNIT; IC50)PinnumberPortname Description29 MU/D Input port for up/down signal from theconnected microphone.32 NOIS Input port for the noise signal from thenoise detector (MAIN unit; D195).31 RSSIInput port for the S-meter signal fromthe demodulator IC (MAIN unit; IC191,pin 12).33 TONIInput port for CTCSS signal from thelow-pass fi lter (MAIN unit, IC1461, pin1).42 TXD1 Output data signals to the USB con-troller (IC550, pin 24).43 RXD1Input port for data signals from theUSB controller (IC550, pin 25) via the(IC553).53 SDA I/O port for data signals from/to theEEPROM (IC54, pin 5).54 SCL Outputs clock signal to the EEPROM(IC54, pin 6).61 BEEP Outputs beep audio signals.71 RESET Input port for reset signal form the re-set IC (IC52, pin 1).72 P2RSCOutputs control signal to the modeswitch (MAIN unit; IC551, pin 5) viathe level converter (IC55).73 P2STCOutputs strobe signal to the 2nd PLLIC (MAIN unit; IC550, pin 3) via thelevel converter (IC55).74 PDATCOutputs the data signal to the 1st and2nd PLL ICs (MAIN unit; IC400, pin 15,IC550, pin 5) via the level converter(IC55).75 PSCKCOutputs clock signal to the 1st and 2ndPLL ICs (MAIN unit; IC400, pin 14,IC550, pin 4) via the level converter(IC55).76 P1STCOutputs strobe signal to the 1st PLLIC (MAIN unit; IC400, pin 16) via thelevel converter (IC55).77 +5ACOutputs control signal to the 5A(Q1345) and D+5 (Q1347) regulatorsvia the level converter (IC55).Low: While the +5 and D+5 regu-lators are activated.78 W/NSCOutputs control signal to the DV/FMfilter switches (MAIN unit; D192,D193) via the level converter (IC55).High: While DV mode is selected.79 ADSWCOutputs control signal to the modeswitches (MAIN unit; IC1411, IC1670,IC1673) via the level converter (IC55).Low: While DV mode is selected.80 TXLED Outputs TX LED control signal.High: During transmit.82 RXLEDOutputs RX LED control signal.High: While receiving or squelch isopened.PinnumberPortname Description85 PCON Outputs control signal to the TX powercontroller (MAIN unit; Q1250).86 ULCK Input port for the PLL unlock signal.High: The PLL circuit is unlocked.87 MMUTOutputs the microphone mute sig-nal to the mute switch (MAIN unit;Q1670).Low: While microphone audio ismuted.93 SCANOutputs scan control signal to thescan switch (Q400).High: While scanning.94 TXSOutputs the T+5, T+3 regulatorcircuits (MAIN unit; Q1336, Q1342)control signal.High: During transmit.95 RXSOutputs the R+5, R+3 regulatorcircuits (MAIN unit; Q1337, Q1343)control signal.High: During receive.96 AMUTOutputs the AF mute signal to the AFmute switch (MAIN unit; Q1550).Low: W h i l e d i g i t a l c o d e / c a l lsign/noise/tone squelch areclosed, the audio level isset to minimum position ortransmitting.102 RMUTOutputs the SQL mute signal to theAF switch (MAIN unit; IC1463, pin 2).High: While noise or tone squelchis closed.103 AFCSW Outputs AFC switch (IC352, pin 5)control signal.105 DACK2 Outputs clock signal to the D/A con-verter (IC57, pin 7).106 DADAT2 Outputs the data signal to the D/Aconverter (IC57, pin 6).107 DACK1 Outputs clock signal to the D/A con-verter (IC56, pin 7).108 DADAT1 Outputs the data signal to the D/Aconverter (IC56, pin 6).128 FSTB Outputs strobe signal to the FPGA IC(IC200).129 MSTRCOutputs strobe signal to the linerC O D E C I C ( I C 1 ) a n d F P G A I C(IC200).130 MDATCOutputs the data signal to the linerC O D E C I C ( I C 1 ) a n d F P G A I C(IC200).131 MCLKCOutputs clock signal to the linerC O D E C I C ( I C 1 ) a n d F P G A I C(IC200).132 MRESCOutputs reset signal to the linerC O D E C I C ( I C 1 ) a n d F P G A I C(IC200).