JETWAY 615DFR1A User Manual

Contents

JETWAY 615DFR1A User Manual Manual pdf 33 page image

30CMOS Setup Utility – Copyright(C) 1984-2000 Award SoftwareSDRAM Timing SettingItem HelpSDRAM CAS Latency Time 3SDRAM Cycle Time Tras/Trc 7/9SDRAM RAS-to-CAS Delay 3SDRAM RAS Precharge Time 3DRAM CTL Buffer strengths WeakDRAM MD Buffer strengths NormalMenu Level >>When set to “Auto”,BIOS will program thisTiming mainly by theSPD method. SPD means“Serial PresenceDetect”, which enablesthe BIOS to accessthe manufacturersettings stored inDRAM module.Move Enter:Select Item +/-/PU/PD:Value F10:Save ESC:Exit F1:General HelpF5:Previous Values F6:Optimized Defaults F7:Standard DefaultsSDRAM CAS Latency TimeWhen synchronous DRAM is installed, the number of clock cycles of CAS latency dependson the DRAM timing. The settings are: 2 and 3.SDRAM Cycle Time Tras/TrcSelect the number of SCLKs for an access cycle. The settings are: 5/7 and 6/8.SDRAM RAS-to-CAS DelayThis field let’s you insert a timing delay between the CAS and RAS strobe signals, used whenDRAM is written to, read from, or refreshed. Fast gives faster performance; and Slow givesmore stable performance. This field applies only when synchronous DRAM is installed in thesystem. The settings are: 2 and 3.SDRAM RAS Precharge TimeIf an insufficient number of cycles is allowed for the RAS to accumulate its charge beforeDRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date. Fastgives faster performance; and Slow gives more stable performance. This field applies onlywhen synchronous DRAM is installed in the system. The settings are: 2 and 3.3-7 Integrated Peripherals