JETWAY 615TCFR3A User Manual

Also see for 615TCF: Manual

Contents

JETWAY 615TCFR3A User Manual Manual pdf 35 page image

32During Enabled, A deferrable CPU cycle will only be Deferred after it has been in a SnoopStall for 31 clocks and another ADS# has arrived. During Disabled, A deferrable CPU cyclewill be Deferred immediately after the GMCH receives another ADS#.Delayed TransactionThe chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.Select Enabled to support compliance with PCI specification version 2.1. The settings are:Enabled and Disabled.On-Chip Video Window SizeThis option enabled/disabled the on-chip video windows size for VGA driver use. Thesettings are: enabled, Disabled.AGP Graphics Aperture SizeThis option determines the effective size of the graphics aperture used in the particular PACconfiguration. The AGP aperture is memory-mapped, while graphics data structure can residein a graphics aperture. The aperture range should be programmed as not cacheable in theprocessor cache, accesses with the aperture range are forwarded to the main memory, thenPAC will translate the original issued address via a translation table that is maintained on themain memory. The option allows the selection of an aperture size of 32MB, 64MB.3-6-1 SDRAM Timing SettingCMOS Setup Utility – Copyright(C) 1984-2000 Award SoftwareSDRAM Timing SettingItem HelpSDRAM CAS Latency Time 3SDRAM Cycle Time Tras/Trc 6/8SDRAM RAS-to-CAS Delay 3SDRAM RAS Precharge Time 3DRAM CTL Buffer strengths NormalDRAM MD Buffer strengths NormalMenu Level >>When set to “Auto”,BIOS will program thisTiming mainly by theSPD method. SPD means“Serial PresenceDetect”, which enablesthe BIOS to accessthe manufacturersettings stored inDRAM module.Move Enter:Select Item +/-/PU/PD:Value F10:Save ESC:Exit F1:General HelpF5:Previous Values F6:Optimized Defaults F7:Standard DefaultsSDRAM CAS Latency Time