JETWAY K8M8M - REV 3.0 User Manual

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JETWAY K8M8M - REV 3.0 User Manual Manual pdf 27 page image

24Video RAM CacheableSelect Enabled allows caching of the video BIOS, resulting in better system performance.However, if any program writes to this memory area, a system error may result. The settingsare: Enabled and Disabled.Memory HoleYou can reserve this area of system memory for ISA adapter ROM. When this area isreserved, it cannot be cached. The user information of peripherals that need to use this area ofsystem memory usually discusses their memory requirements. The settings are: Enabled andDisabled.3-6-1 DRAM Timing SettingsPhoenix – AwardBIOS CMOS Setup UtilityDRAM Timing SettingsItem HelpHypertransport Link Frequency 800 MHzHYpertransport Link Width in 16 bitHypertransport Link Width Out 16 bitAuto Configuration Autox DRAM CAS Latency CL=2.5x RAS Active Time 8 Bus Clocksx RAS Precharge Time 3 Bus Clocksx RAS to CAS Delay 3 Bus Clocksx Bank Interleave EnabledDRAM Command Rate 1T(By CPU)Menu Level >>↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General HelpF5:Previous Values F6:Optimized Defaults F7:Standard DefaultsRAS Active TimeThis field let’s you insert a timing delay between the CAS and RAS strobe signals, used whenDRAM is written to, read from, or refreshed. Fast gives faster performance; and Slow givesmore stable performance. This field applies only when synchronous DRAM is installed in thesystem. The settings are: 2T and 3T.RAS Precharge TimeIf an insufficient number of cycles is allowed for the RAS to accumulate its charge beforeDRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date. Fastgives faster performance; and Slow gives more stable performance. This field applies onlywhen synchronous DRAM is installed in the system. The settings are: 2T and 3T.CAS LatencyWhen synchronous DRAM is installed, the number of clock cycles of CAS latency dependson the DRAM timing. The settings are: 2T and 2.5T.