JETWAY V623DMR1A User Manual
                                                | |
Contents
| 
27CMOS Setup Utility – Copyright(C) 1984-2003 Award SoftwareAGP Timing SettingsItem HelpAGP Aperture Size 64MBAGP Mode 4XAGP Fast Write DisabledAGP Master 1 WS Write DisabledAGP Master 1 WS Read DisabledCPU to AGP Post Write EnabledAGP Delay Transaction EnabledVGA Share Memory Size 32MBMenu Level >>↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General HelpF5:Previous Values F6:Optimized Defaults F7:Standard Defaults3-6-3 PCI Timing SettingsCMOS Setup Utility – Copyright(C) 1984-2003 Award SoftwarePCI Timing SettingsItem HelpPCI Master 1 WS Write DisabledPCI Master 1 WS Read DisabledCPU to PCI Post Write DisabledPCI Delay Transaction Enabled Menu Level >>↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General HelpF5:Previous Values F6:Optimized Defaults F7:Standard DefaultsPCI Delay TransactionThe chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.Select Enabled to support compliance with PCI specification version 2.1. The settings are:Enabled and Disabled.3-7 Integrated PeripheralsCMOS Setup Utility – Copyright(C) 1984-2003 Award SoftwareIntegrated PeripheralsItem HelpOnChip IDE Function Press EnterOnChip Device Function Press EnterOnChip SIO Function Press EnterInit Display First PCI Slot Menu Level >↑↓→← Move Enter:Select Item +/-/PU/PD:Value F10:Save ESC:Exit F1:General HelpF5:Previous Values F6:Optimized Defaults F7:Standard DefaultsOnChip IDE Function |
Related manuals for JETWAY V623DMP
manualsdatabase
Your AI-powered manual search engine