DV-502/503/DVF-3050/35508CIRCUIT DESCRIPTIONPin No. Pin Name I/O Description1 BCK I Audio data bit clock input.2 DATA I Audio data digital input.3 LRCK I Audio data latch enable input.4 DGND - Digital ground.5 VDD - Digital power supply (+3.3V).6 VCC - Analog power supply (+5V).7 VOUTL O Analog output for L-channel.8 VOUTR O Analog output for R-channel.9 AGND - Analog ground.10 VCOM - Common voltage decoupling.11 ZEROR O Zero flag output for R-channel.12 ZEROL O Zero flag output for L-channel.13 MD I Mode control data input.14 MC I Mode control clock input.15 ML I Mode control latch input.16 SCK I System clock input.2-2 D/A Converter : PCM1748(IC801)Pin No. Pin Name I/O Description38 CLK I The system clock input. all other inputs are registered to the SDRAM onthe rising edge of CLK.37 CKE - Controls internal clock signal and when deactivated, the SDRAM will be oneof the states among power down, suspend or self refresh.19 CS - Enables or disables all inputs except CLK, CKE, and DQM.20,21 BA0,BA1 - Selects bank to be activated during RAS activity.Selects bank to be read/written during CAS activity.23~26 A0~A11 - Row address : RA0~RA11, Column address : CA0~CA729~35 Auto-precharge flag : A1018 WE,CAS,RAS - WE, CAS and RAS define the operation.15,39 LDQM,UDQM I/O Controls output buffers in read mode and masks input data in write mode.2,4,5,7,8,10,11,13,42 DQ0~DQ15 I/O Multiplexed data input/output pin.44 45,47,4850,51,539 VDD/VSS - Power supply for internal circuits and input buffers.10 VDDQ/VSSQ - Power supply for output buffers.11 NC - Unused2-3 64 Bit SDRAM : KS641632D(IC301)Block Diagram for D/A ConverterBCK SerialLRCK Input Vout LDATA I/F Output Amp andLow-pass Filter8XOversampling EnhancedDigital Filter Multi-levelVcomML Function with Delta-SigmaFunction ModulatorMC Control ControllerOutput Amp andMDI I/F Low-pass Filter Vout RSystem ClockSCKSystemClockManager\Zero Detect Power SupplyZERO LZERO RVDDDGNDVCCAGNDDACDAC