Kenwood KDC-MP6090R Service Manual

Also see for KDC-MP6090R: Instruction manual

Contents

KDC-MP6090R/MP7018/MP801710CIRCUIT DESCRIPTION (MP3)MP3 DSP IC : STA013 (X32-5080 : IC5) OUT SIDE VIEW SINGLE CHIP MPEG2 LAYER 3 DECODER SUP-PORTING.Note (Z919 is guaranteed to the MPEG 1.0 Layer 3.)• All features specified for Layer in ISO/IEC11172-3(MPEG 1 Audio)• All features specified for Layer 3 in ISO/IEC13818-3.2(MPEG 2 Audio)• Lower sampling frequencies syntax extension, (not spec-ified by ISO) called MPEG2.5 DECODES LAYER III STEREO CHANNELS, DUALCHANNEL, SINGLE CHANNEL (MONO) SUPPORTING ALL THE MPEG 1 & 2 SAMPLING FRE-QUENCIES AND THE EXTENSION TO MPEG 2.5: 48,44.1, 32, 24, 22.05, 16, 12, 11.025, 8kHz ACCEPTS MPEG 2.5 LAYER III ELEMENTARY COM-PRESSED BIT STREAM WITH DATA RATE FROM 8Kbit/s UP TO 320 Kbit/s DIGITAL VOLUME CONTROL DIGITAL BASS & TREBLE CONTROL SERIAL BITSTREAM INPUT INTERFACE ANCILLARY DATA EXTRACTION VIA I2 C INTERFACE SERIAL PCM OUTPUT INTERFACE (I2C AND OTHERFORMATS) PLL FOR INTERNAL CLOCK AND FOR OUTPUT PCMCLOCK GENERATION LOW POWER CONSUMPTION: 85mW AT 2.4V CRC CHECK AND SYNCHRONISATION ERRORDETECTION WITH SOFTWARE INDICATORS I2C CONTROL BUS LOW POWER 3.3V CMOS TECHNOLOGY 10MHz,14.31818 MHz, OR 14.7456MHz EXTERNALINPUT CLOCK OR BUILT-IN INDUSTRY STANDARDXTAL OSCILLATOR DIFFERENT FREQUENCIES MAYBE SUPPORTED UPON REQUEST TO STMNote EXTERNAL CLOCK: 10MHz APPLICATIONS PC SOUND CARDS MULTIMEDIA PLAYERS DESCRIPTIONThe STA013 is a fully integrated high flexibility MPEG LayerIII Audio Decoder, capable of decoding Layer 3 com-pressed elementary streams, as specified in MPEG 1 andMPEG 2 ISO standards.The device decoders also elemen-tary streams compressed by using low sampling rates, asspecified by MPEG 2.5.STA013 receives the input data through a Serial InputInterface.The decoded signal is a stereo,mono, or dualchannel digital output that can be sent directly to a D/A con-verter, by the PCM Output Interface.This interface is soft-ware programmable to adapt the STA013 digital output tothe most common DACs architectures used on the market.The functional STA013 chip partitioning is described in Fig. 1.I2C CONTROLSERIALINPUTINTERFACEBUFFER PARSERMPEG 2.5LAYER IIIDECODERCORECHANNELCONFIG.&VOLUMECONTROLOUTPUTBUFFERPCMOUTPUTINTERFACE101195268 28 21 20 12 24 253 467SYSTEM & AUDIO CLOCKS TEST INTERFACERESET SDA SCLSDISCKRBIT_ENSRC INT OUT_CLK/DATA_REQ XTI XTO OCLK TESTEN SCANENSDOSCKTLRCKTFig. 1 Block diagram: MPEG 2.5 Layer # Decoder hardware Partitioning