6TK-2107TK-260 :K, K2Item RatingNominal center frequency 38.850MHzPass band width ± 7.5kHz or more at 3dB40dB stop band width ± 40.0kHz or lessRipple 1.0dB or lessInsertion loss 3.0dB or lessGuaranteed attenuation 80dB or more at fo -1000kHzTerminal impedance 1200Ω / 1.4PFItem RatingNominal center frequency 450kHz6dB band width ± 7.5kHz or more50dB band width ± 15kHz or lessRipple 2.0dB or less at fo ± 5kHzInsertion loss 6.0dB or lessGuaranteed attenuation 35.0dB or more at fo ± 100kHzTerminal impedance 1.5 kΩXF200:L71-0535-05 CF200:L72-0979-055) SquelchPart of the AF signal from the IC enters the FM IC again,and the noise component is amplified and rectified by a filterand an amplifier to produce a DC voltage corresponding to thenoise level.The DC signal from the FM IC goes to the analog port of themicroprocessor (IC403). IC403 determines whether to outputFig. 3 AF Amplifier and squelchFM IF IC IC200IF AMP DETDET HPFAMPLPFIC301QT/DQTQ303W/N SWIC403MPUBUSYMUTEAFCOTI656762AF AMPIC300LPF HPFQ302SWIC302AF PA AMP Q307SWSWSPQ304, 305, 306sounds from the speaker by checking whether the inputvoltage is higher or lower than the preset value.To output sounds from the speaker, IC403 sends a highsignal to the MUTE and AFCO Iines and turns IC302 onthrough Q302, Q304, Q305, Q306 and Q307.(See Fig. 3)6) Receive signalingQT/DQT300 Hz and higher audio frequencies of the output signalfrom IF IC are cut by a low-pass filter (IC301). The resultingsignal enters the microprocessor (IC403). IC403 determineswhether the QT or DQT matches the preset value, andcontrols the MUTE and AFCO and the speaker output soundsaccording to the squelch results.3. PLL frequency synthesizerThe PLL circuit generates the first local oscillator signal forreception and the RF signal for transmission.1) PLLThe frequency step of the PLL circuit is 5 or 6.25kHz.A 12.8MHz reference oscillator signal is divided at IC1 by a fixedcounter to produce the 5 or 6.25kHz reference frequency. Thevoltage controlled oscillator (VCO) output signal is bufferamplified by Q6, then divided in IC1 by a dual-moduleprogrammable counter . The divided signal is compared in phasewith the 5 or 6.25kHz reference signal in the phase comparator inIC1. The output signal from the phase comparator is filtreredthrough a low-pass filter and passed to the VCO to control theoscillator frequency. (See Fig.4)CIRCUIT DESCRIPTION