TKR-840CIRCUIT DESCRIPTIONC213L205C285SCC225rJ 10. 2Mlh osc! .;Q201D201.202I FREQ. CONTROL I'---;::======-.i__:;�-4--Q18. IC200C204IC201§1SUB PLL CV"'0R203 R202 R209 �..0Nu..0Nu�--+--L201. Ql08�----+--------+--+--+-�1 �•·�2=MH='-+-----Q241�--"�=�-+----JC4(Q4)�------+-+----�D�P ------sc�--�c�.-----JCS(4PINL 1Cl0l(DATL 1C202(SDAr>�---�-----JCSClOPIN), lC101 CCLK), IC202(SCLK)Fig.2 Transmitter reference PLL circuit2.3 Transmitter DDS circuitThe transmitter DDS circuit produces the referencefrequency signal (4.5 MHz) for the transmitter main PLL andmodulates the low-frequency components of digital pagermodulation. This circuit consists of 0241, IC202, IC107, 0207,0240, and 0242. The 19.2MHz signal coming from thetransmitter sub PLL is amplified by 0241 and fed to IC202.IC202 produces the 4.5MHz reference frequency signal forthe transmitter main PLL based on the 19.2MHz signal. Sincethe comparison frequency of the transmitter main PLL is 100kHz, the PLL frequency step is 100 kHz. However, fineSB'"'..NuC21 BNu1C201 (AUXI ). L2os---1t--t-...._t£R251frequency steps, such as 2.5kHz and 1.25kHz, can be usedbecause the DDS output frequency is variable. IC202 performsbinary FSK modulation. Digital pager modulation isimplemented by applying low-range modulation to DDS andhigh-range modulation to the transmitter main PLL. There is atwo-stage Butterworth filter (cutoff frequency: 3.2kHz)consisting of IC102 in the high-range modulation line. TheIC102 shift input is delayed by IC107 and IC207 to maintainphase balance between the low and high ranges. (See thelevel adjustment circuit description.)Q240iBUFFERl�ElR.208+ 0 ' :; IC3 (VI7)> .,PSLOPSLlFSEL t------<>---�FSYN t-"L=EN�-'VV'�IC202looslICSC4PIN), IClOl< DAT).IC201(DATA)�Q207I INVERTER!., .,' +< < >4lCSCIOPINL IC101 CCLK). '-+-----"D'-'-TE"--- IC4CQ3)IC201 (CLOCK)Fig.3 Transmitter DDS circuit 25