r~CIRCUIT DESCRIPTION2. LO2 (PLL loop)The VCO of IC10 (KCH14) generates a signal of62.35MHz. The 10-MHz reference frequency is ap-plied to pin 5 of IC101 (CXD1225M), and is divided by200 (800 in FM mode) t o produce a 50-kHz (12.5-kHz inFM mode) comparison frequency. The output fromthe VCO is applied t o pin 11 of IC101, and is divided by1247 (4988 in FM mode). It is then compared with the50-kHz (12.5-kHz in F M mode) reference signal by thephase comparator t o lock the VCO frequency. Divideratio data is supplied by the digital unit.The output is amplified by amplifier Q18 (2SC2954)and passes through a low-pass filter. The VCO ismodulated in FM mode.c 3. LO1 (PLL l w p lQ1, 0 3 (2SK508NV) in the X58-4120-00 are VCOs.0 1 generates a signal of 113.045 t o 123.044MHz; andQ3, a signal of 123.045 t o 133.045MHz. K typeQ3 (2SK508NV) in the X58-4120-00 are VCO. Q3generates a signal of 123.045 t o 127.045MHz. E typeThe 10-MHz reference signal is input t o pin 5 oflCl 1 (CXD1225M) and is divided by 20 t o produce a500-kHz comparison frequency. The output signalfrom the VCO is mixed with a 75.045- t o 75.545-MHzsignal from the PLL (described later) to produce a 38.0-t o 57.5-MHz signal. It is input to pin 11 of IC11, di-vided, and compared with the 500-kHz signal by thephase comparator, and the VCO frequency is locked.Divide ratio data is supplied by the digital unit.The 20-MHz reference signal is input t o DDSl (X58-4020-OO), and the output signal is mixed with a 4-MHzsignal by IC4 t o generate a signal of 4.455 to4.955MHz(in 5- or 200-Hz steps). The signal is mixed with the 80-MHz signal ( 4 x 20-MHz reference frequency) by IC5(SN16913P) t o produce a 75.045 to 75.545MHz signal(in 5- or 200-Hz steps).4. CARThe 20-MHz reference signal is input to DDS2 (X58-4020-OO), and the output signal is mixed by IC7 (SN16913P) with the 10MHz signal divided by IC2 t o p r oduce a 10.695-MHz signal. This signal passes throughthe band-pass filter and amplifier and is output for localoscillation and detection.5. DDSThe DDS is the same as that used in the TS-50.Fig. 2 PLL circuit frequency configuration