ML62Q1722 Reference Board User’s ManualFEBL62Q1722RB 42.2. Connection for EASE1000 (CNE)EASE1000 can be used if J1 and J2 jumper are set to “CNE”.Fig. 3 EASE1000 Interface[Note]P00/TEST0 pin:P00/TEST0 pin of ML62Q1722 is initially set as a pull-up input modeWhen using EASE1000, do not set it as an output mode by using an application program, otherwise EASE1000cannot communicate with the ML62Q1722.CNEML62Q1722RESET_NP00/TEST010kVDDCJ1USRCNE RST_OUT/SCKSDATA57CN1RESET_NP00/TEST067J2CUSRCNE

Overview

ML62Q1722 Reference Board Outline Diagram

Function of ML62Q1722 Reference Board

Connection for EASE1000 (CNE)

LED (P20, P21, P22)

C1, C2, VL1, VL2, VL3

User Interface

Precaution for usage

PCB specification, BOM and Schematic

ML62Q1722 Reference Board BOM

revision history

LAPIS Semiconductor ML62Q1722 User Manual

FEUL62Q1000

Features

BLOCK DIAGRAM

Pin Layout

PIN LIST

PIN DESCRIPTION

TERMINATION OF UNUSED PINS

General Description

Wait mode and No-wait mode

Coprocessor

List of Coprocessor General-purpose Registers

How to Use Multiplier/Divider

Memory Space

Configuration

Data Memory Space

Description of Registers

Data Segment Register (DSR)

Flash Remap Address Register (REMAPADD)

Remapping Function

Description of Remapping Function

Code Option Remap

Reset Function

Reset Status Register (RSTAT)

Safety Function Reset Status Register (SRSTAT)

Description of Operation

System Reset Mode

Power-On Reset

Stop Code Acceptor (STPACP)

Standby Control Register (SBYCON)

Software Reset Acceptor (SOFTRACP)

Software Reset Control Register (SOFTRCON)

Block Clock Control Register 0 (BCKCON0)

Block Clock Control Register 1 (BCKCON1)

Block Clock Control Register 2 (BCKCON2)

Block Clock Control Register 3 (BCKCON3)

Block Reset Control Register 0 (BRECON0)

Block Reset Control Register 1 (BRECON1)

Block Reset Control Register 2 (BRECON2)

Block Reset Control Register 3 (BRECON3)

HALT-H mode

STOP mode

STOP-D Mode

Operation of Each Function in Standby Mode

Block Control Function

Interrupts

Interrupt Enable Register 01 (IE01)

Interrupt Enable Register 23 (IE23)

Interrupt Enable Register 45 (IE45)

Interrupt Enable Register 67 (IE67)

Interrupt Request Register 01 (IRQ01)

Interrupt Request Register 23 (IRQ23)

Interrupt Request Register 45 (IRQ45)

Interrupt Request Register 67 (IRQ67)

Interrupt Level Control Enable Register (ILEN)

Current Interrupt Level Management Register (CIL)

Interrupt Level Control Register 0 (ILC0)

Interrupt Level Control Register 1 (ILC1)

Interrupt Level Control Register 2 (ILC2)

Interrupt Level Control Register 3 (ILC3)

Interrupt Level Control Register 4 (ILC4)

Interrupt Level Control Register 5 (ILC5)

Interrupt Level Control Register 6 (ILC6)

Interrupt Level Control Register 7 (ILC7)

Maskable Interrupt Processing

Notes on Interrupt Routine (with Interrupt Level Control Disabled)

Flow Charts When Interrupt Level Control Is Enabled

How To Write Interrupt Processing When Interrupt Level Control Enabled

Interrupt Disable State

Clock Generation Circuit

List of Pins

High-Speed Clock Mode Register (FHCKMOD)

Low-speed Clock Mode Register (FLMOD)

Clock Control Register (FCON)

High-Speed Clock Wake-up Time Setting Register (FHWUPT)

Backup Control Register (FBUCON)

ML62Q1722