Lattice Semiconductor USB3-GbE VIP I/O Board User Manual

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Lattice Semiconductor USB3-GbE VIP I/O Board User Manual Manual pdf 8 page image

USB3-GbE VIP I/O BoardEvaluation Board User Guide© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.8 FPGA-EB-02016-1.0Table 3.2. Connector J2J1 Connector Pin Signal Name Device - pin Description1, 2, 3, 4 3.3V — —5 FX3_D0 FX3 - DQ0 —6 FX3_D3 FX3 - DQ3 —7 FX3_D4 FX3 - DQ4 —8 FX3_D6 FX3 - DQ6 —9 FX3_D15 FX3 - DQ15 —10 FX3_D8 FX3 - DQ8 —11 FX3_D7 FX3 - DQ7 —12 FX3_D10 FX3 - DQ10 —13 FX3_PCKTEND_N FX3 - CTL7_PKTEND —14 FX3_D12 FX3 - DQ12 —15 FX3_SLRD_N FX3 - CTL3_SLRD —16 FX3_D11 FX3 - DQ11 —17 FX3_D14 FX3 - DQ14 —18 FX3_D13 FX3 - DQ13 —19 FX3_PCLK FX3 - PCLK_CLK— —20, 21 GND — —22 FX3_D9 FX3 - DQ9 —23 FX3_A1 FX3 - CTL11_A1 —24 FX3_SLCS_N FX3 - CTL0_SLCS —25 FX3_A0 FX3 - CTL12_A0 —26 FX3_SLWR_N FX3 - CTL1_SLWR —27 FX3_D17 FX3 - DQ12 —28 RGMII_RXCTRL DP -RX_DV/RX_CTRL RECEIVE DATA VALID or RECEIVE CONTROL29 FX3_D20 FX3 - DQ20 —30 RGMII_TXCTRL DP -TX_EN/TX_CTRL TRANSMIT ENABLE or TRANSMIT CONTROL31 FX3_D23 FX3 - DQ23 —32 RGMII_RXD3 DP -RX_D3 RECEIVE DATA Bit 333 FX3_D5 FX3 - DQ5 —35 FX3_D1 FX3 - DQ1 —36 RGMII_RXD1 DP -RX_D1 RECEIVE DATA Bit 137 FX3_D2 FX3 - DQ2 —38 RGMII_RXD0 DP -RX_D0 RECEIVE DATA Bit 039, 40 GND — —41 FX3_FLAG_A FX3 - CTL4_FLAGA —42 RGMII_TXCLK DP -GTX_CLK GMII and RGMII TRANSMIT CLOCK43 FX3_SLOE_N FX3 - CTL2_SLOE —44 RGMII_TXD0 DP -TX_D0 GMII TRANSMIT DATA Bit 045 FX3_FLAG_B FX3 - CTL5_FLAGB—46 RGMII_TXD1 DP -TX_D1 GMII TRANSMIT DATA Bit 147 FX3_D30 FX3 - DQ30 —48 RGMII_TXD2 TX_D2 GMII TRANSMIT DATA Bit 249 TP1 —50 RGMII_TXD3 TX_D3 GMII TRANSMIT DATA Bit 351 TP2 —52 RGMII_RXCLK DP -RX_CLK RECEIVE CLOCK54 TP3 —53, 55 ,56 GND — —57,58, 59, 60 2.5V — —