Lattice Semiconductor iCE40 SPRAM Series Technical Note

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Lattice Semiconductor iCE40 SPRAM Series Technical Note Manual pdf 7 page image

iCE40 SPRAM Usage GuideTechnical Note© 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names aretrademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.TN1314-1.0 7Use Cases for User Primitive SB_SPRAM256KA4.This section describes the use cases of the SB_SPRAM256KA RAM blocks while instantiating, inferring, and cascadingthese blocks.4.1. Instantiating MemoriesSB_SPRAM256KA primitive can be directly instantiated using both Verilog and VHDL at the top level. An example ofinstantiating SB_SPRAM256KA RAM using Verilog:// spram256 user modules //SB_SPRAM256KA ramfn_inst1(.DATAIN(DATAIN),.ADDRESS(ADDRESS),.MASKWREN(MASKWREN),.WREN(WREN),.CHIPSELECT(CHIPSELECT),.CLOCK(CLOCK),.STANDBY(STANDBY),.SLEEP(SLEEP),.POWEROFF(POWEROFF),.DATAOUT(DATAOUT_A))SB_SPRAM256KA ramfn_inst2(.DATAIN(DATAIN),.ADDRESS(ADDRESS),.MASKWREN(MASKWREN),.WREN(WREN),.CHIPSELECT(CHIPSELECT),.CLOCK(CLOCK),.STANDBY(STANDBY),.SLEEP(SLEEP),.POWEROFF(POWEROFF),.DATAOUT(DATAOUT_B))4.2. Inferring MemoriesThe memory also supports memory inferring where a behavioral code for the SPRAM is synthesized in iCEcube2 tocreate the RAM using the RAM primitives of ICE40 device. In order to use SB_SPRAM256KA RAM blocks, users can usesyn_ramstyle attribute.The power save states (Standby, Sleep, and Power Off States) are not available when inferring the RAM. Whenimplementing the inferred RAM using SB_SPRAM256KA primitives, software should tie off the STANDBY, SLEEP andSHUTDOWN ports to “0”. If power save features are desired, then users should use the method of instantiation andconnect these ports as per design requirements.4.3. Output Pipeline RegistersThe SB_SPRAM256KA does not include output registers.When desired, pipeline registers are required to be implemented in the fabric. While inferring the RAM, the softwareshould implement the output pipeline registers in the fabric.