NXP Semiconductors MC92602 User Manual

Contents

MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3iv Freescale SemiconductorParagraph PageNumber Title NumberChapter 3Laboratory Equipment and Quick Setup Evaluation3.1 Recommended Laboratory Equipment ............................................................................ 3-13.2 Quick Setup Data-Eye Diagram ...................................................................................... 3-23.2.1 Quick Setup Data-Eye Generation and Observation ................................................... 3-33.2.1.1 Equipment Setup...................................................................................................... 3-33.2.1.2 Parallel Input Connections....................................................................................... 3-43.2.2 Basic Eye ObservationóTest Procedure..................................................................... 3-53.2.3 Quick Setup Bit Error Rate Checking.......................................................................... 3-63.2.3.1 Equipment Setup...................................................................................................... 3-63.2.3.2 Parallel I/O Connections.......................................................................................... 3-73.2.3.3 Quick Setup BERC Test Procedure ......................................................................... 3-7Chapter 4Test Setups4.1 Serial Link Verification Using a Serial Bit Error Rate Tester (BERT) ............................ 4-14.1.1 Test Setup for Full-Speed Mode .................................................................................. 4-24.1.2 Test Setup for Half-Speed Mode ................................................................................. 4-24.2 Jitter Testing..................................................................................................................... 4-34.2.1 Jitter Test System Calibration ...................................................................................... 4-34.2.2 Reference Clock Jitter Transfer Test............................................................................ 4-44.2.3 Reference Clock Jitter Tolerance Test ......................................................................... 4-54.2.4 Data Jitter Tolerance Test............................................................................................. 4-6Appendix AConnector SignalsA.1 Input: 2 × 10 (0.100") Connectors.................................................................................... A-1A.1.1 Control Signal Input Connectors ................................................................................ A-1A.1.2 Transmitter Parallel Data Input Connectors ............................................................... A-3A.2 Output: 2 × 20 (0.100") Connectors................................................................................. A-4A.3 TEST_0 Connector ......................................................................................................... A-5Appendix BParts ListB.1 Design Verification Board Parts List ...............................................................................B-1