NXP Semiconductors MIMXRT1170HDUG Hardware Development Manual

Table 11. ROM Bootloader Peripheral PinMux (continued)Peripheral Instance Port (IO function) PAD Mode Note2 USDHC2_CD_B GPIO_AD_26 ALT11USDHC2_WP GPIO_AD_27 ALT11USDHC2_VSELECT GPIO_AD_28 ALT11USDHC2_DATA3 GPIO_SD_B2_00 ALT0USDHC2_DATA2 GPIO_SD_B2_01 ALT0USDHC2_DATA1 GPIO_SD_B2_02 ALT0USDHC2_DATA0 GPIO_SD_B2_03 ALT0USDHC2_CLK GPIO_SD_B2_04 ALT0USDHC2_CMD GPIO_SD_B2_05 ALT0USDHC2_RESET_B GPIO_SD_B2_06 ALT0USDHC2_DATA4 GPIO_SD_B2_08 ALT0USDHC2_DATA5 GPIO_SD_B2_09 ALT0USDHC2_DATA6 GPIO_SD_B2_10 ALT0USDHC2_DATA7 GPIO_SD_B2_11 ALT0FlexSPI1 1 FLEXSPI1_B_DATA3GPIO_SD_B2_00 ALT1 QSPI memory attached toFlexSPI is a primary boot option.Refer to Serial NOR FlashBoot via FlexSPI in ReferenceManual for more information.The ROM will read the 512-byte FlexSPI NOR configurationparameters described in FlexSPISerial NOR Flash Boot OperationReference Manual using the non-italicized pins.Note: These pins are a secondarypinout option for FlexSPI serialNOR flash bootFLEXSPI1_B_DATA2GPIO_SD_B2_01 ALT1FLEXSPI1_B_DATA1GPIO_SD_B2_02 ALT1FLEXSPI1_B_DATA0GPIO_SD_B2_03 ALT1FLEXSPI1_B_SCLK GPIO_SD_B2_04 ALT1FLEXSPI1_B_DQS GPIO_SD_B1_05 ALT8FLEXSPI1_B_SS0_B GPIO_SD_B1_04 ALT8FLEXSPI1_B_SS1_B GPIO_SD_B1_03 ALT9FLEXSPI1_A_DQS GPIO_SD_B2_05 ALT1FLEXSPI1_A_SS0_B GPIO_SD_B2_06 ALT1FLEXSPI1_A_SS1_B GPIO_SD_B1_02 ALT9FLEXSPI1_A_SCLK GPIO_SD_B2_07 ALT1FLEXSPI1_A_DATA0GPIO_SD_B2_08 ALT1FLEXSPI1_A_DATA1GPIO_SD_B2_09 ALT1Table continues on the next page...NXP SemiconductorsBoot, reset, and miscellaneousHardware Development Guide for the MIMXRT1160/1170 Processor , Rev. 2, 09/2021User Guide 14 / 24